cdf2018-principal/fpga/principal.ucf

# CLK
NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;


# BTN
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;

# IO<10>
NET "RX" LOC = "P85" | IOSTANDARD = LVTTL ;

# IO<11>
NET "TX" LOC = "P84" | IOSTANDARD = LVTTL ;

# IO<12>
NET "LEFTCHA" LOC = "P83" | IOSTANDARD = LVTTL ;

# IO<13>
NET "LEFTCHB" LOC = "P78" | IOSTANDARD = LVTTL ;

# IO<14>
NET "RIGHTCHA" LOC = "P77" | IOSTANDARD = LVTTL ;

# IO<15>
NET "RIGHTCHB" LOC = "P65" | IOSTANDARD = LVTTL ;

# IO<16>
NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ;

# IO<17>
NET "FRONTECHO" LOC = "P71" | IOSTANDARD = LVTTL ;

# IO<18>
NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ;

# IO<19>
NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ;

# IO<20>
NET "ENA" LOC = "P5" | IOSTANDARD = LVTTL ;

# IO<21>
NET "IN1ENC" LOC = "P4" | IOSTANDARD = LVTTL ;

# IO<22>
NET "IN2" LOC = "P6" | IOSTANDARD = LVTTL ;

# IO<23>
NET "ENB" LOC = "P98" | IOSTANDARD = LVTTL ;

# IO<24>
NET "IN3END" LOC = "P94" | IOSTANDARD = LVTTL ;

# IO<25>
NET "IN4" LOC = "P93" | IOSTANDARD = LVTTL ;

# NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
# NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
# NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
# NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;