diff --git a/fpga/Principal.vhd b/fpga/Principal.vhd index ac80d6d..74baa08 100644 --- a/fpga/Principal.vhd +++ b/fpga/Principal.vhd @@ -82,6 +82,11 @@ architecture Behavioral of Principal is ); end component; + -- PWM clock + signal pwmClk : std_logic := '0'; + signal pwmCounter : integer := 0; + constant PWM_DIVIDER : integer := 1024; + -- Motor controller signal enAd : std_logic_vector(7 downto 0); signal in1enCd : std_logic_vector(7 downto 0); @@ -151,6 +156,17 @@ begin reset <= BTN; + pwmClkGenerator: process (clk) begin + if rising_edge(clk) then + if (pwmCounter >= PWM_DIVIDER) then + pwmClk <= not pwmClk; + pwmCounter <= 0; + else + pwmCounter <= pwmCounter + 1; + end if; + end if; + end process; + leftCoder: hedm port map ( clk => CLK, chA => LEFTCHA, @@ -205,26 +221,26 @@ begin -- done => done ); enAp : PWM port map ( - clk => CLK, + clk => pwmClk, data => enAd, pulse => ENA ); in1enCp : PWM port map ( - clk => CLK, + clk => pwmClk, data => in1enCd, pulse => IN1ENC ); IN2 <= in2d; enBp : PWM port map ( - clk => CLK, + clk => pwmClk, data => enBd, pulse => ENB ); in3enDp : PWM port map ( - clk => CLK, + clk => pwmClk, data => in3enDd, pulse => IN3END ); diff --git a/fpga/Principal_tb.gtkw b/fpga/Principal_tb.gtkw index 26847f4..269f037 100644 --- a/fpga/Principal_tb.gtkw +++ b/fpga/Principal_tb.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI -[*] Tue May 1 05:22:50 2018 +[*] Tue May 1 19:20:55 2018 [*] [dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.ghw" -[dumpfile_mtime] "Tue May 1 05:18:35 2018" -[dumpfile_size] 6534540 +[dumpfile_mtime] "Tue May 1 19:20:01 2018" +[dumpfile_size] 5276557 [savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/Principal_tb.gtkw" [timestart] 0 [size] 1600 862 [pos] -1 -1 -*-43.492355 11010000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-42.492355 11010000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] top. [treeopen] top.principal_tb. [treeopen] top.principal_tb.dut. @@ -103,6 +103,12 @@ top.principal_tb.dut.backcapt.distancecounter @420 [color] 3 top.principal_tb.dut.back +@8421 +[color] 5 +top.principal_tb.dut.pwmcounter +@29 +[color] 5 +top.principal_tb.dut.pwmclk @22 [color] 5 #{top.principal_tb.dut.enad[7:0]} top.principal_tb.dut.enad[7] top.principal_tb.dut.enad[6] top.principal_tb.dut.enad[5] top.principal_tb.dut.enad[4] top.principal_tb.dut.enad[3] top.principal_tb.dut.enad[2] top.principal_tb.dut.enad[1] top.principal_tb.dut.enad[0] diff --git a/fpga/pwm.vhd b/fpga/pwm.vhd index 64391be..960d758 100644 --- a/fpga/pwm.vhd +++ b/fpga/pwm.vhd @@ -13,8 +13,8 @@ entity PWM is end PWM; architecture Behavioral of PWM is - signal accuI : integer; - signal dataI : integer; + signal accuI : integer := 0; + signal dataI : integer := 0; begin dataI <= to_integer(unsigned(data)); @@ -22,9 +22,9 @@ begin process(clk, data) begin if rising_edge(clk) then - accuI <= accuI mod 256 + dataI + 1; + accuI <= accuI mod 256 + dataI; end if; end process; - pulse <= '1' when accuI >= 256 else '0'; + pulse <= '1' when accuI > 256 else '0'; end Behavioral; diff --git a/fpga/pwm_tb.gtkw b/fpga/pwm_tb.gtkw new file mode 100644 index 0000000..016039e --- /dev/null +++ b/fpga/pwm_tb.gtkw @@ -0,0 +1,31 @@ +[*] +[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI +[*] Tue May 1 17:18:48 2018 +[*] +[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/pwm_tb.ghw" +[dumpfile_mtime] "Tue May 1 17:16:31 2018" +[dumpfile_size] 11137 +[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/pwm_tb.gtkw" +[timestart] 0 +[size] 1600 862 +[pos] -1 -1 +*-29.567368 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.pwm_tb. +[treeopen] top.pwm_tb.dut. +[sst_width] 213 +[signals_width] 257 +[sst_expanded] 1 +[sst_vpaned_height] 244 +@28 +top.pwm_tb.clk +@22 +#{top.pwm_tb.data[7:0]} top.pwm_tb.data[7] top.pwm_tb.data[6] top.pwm_tb.data[5] top.pwm_tb.data[4] top.pwm_tb.data[3] top.pwm_tb.data[2] top.pwm_tb.data[1] top.pwm_tb.data[0] +@8421 +top.pwm_tb.dut.datai +@88420 +top.pwm_tb.dut.accui +@28 +top.pwm_tb.dut.pulse +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/fpga/pwm_tb.vhd b/fpga/pwm_tb.vhd new file mode 100644 index 0000000..950ca80 --- /dev/null +++ b/fpga/pwm_tb.vhd @@ -0,0 +1,61 @@ +-- Testbench automatically generated online +-- at http://vhdl.lapinoo.net +-- Generation date : 1.5.2018 17:12:00 GMT + +library ieee; +use ieee.std_logic_1164.all; + +entity PWM_tb is +end PWM_tb; + +architecture tb of PWM_tb is + + component PWM + port (clk : in std_logic; + data : in std_logic_vector (7 downto 0); + pulse : out std_logic); + end component; + + signal clk : std_logic; + signal data : std_logic_vector (7 downto 0); + signal pulse : std_logic; + + constant TbPeriod : time := 20 ns; + signal TbClock : std_logic := '0'; + signal TbSimEnded : std_logic := '0'; + +begin + + dut : PWM + port map (clk => clk, + data => data, + pulse => pulse); + + -- Clock generation + TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; + + clk <= TbClock; + + stimuli : process + begin + data <= x"00"; + wait for 100 * TbPeriod; + + data <= x"FF"; + wait for 100 * TbPeriod; + + data <= x"80"; + wait for 100 * TbPeriod; + + data <= x"e6"; + wait for 100 * TbPeriod; + + data <= x"3c"; + wait for 100 * TbPeriod; + + -- Stop the clock and hence terminate the simulation + TbSimEnded <= '1'; + wait; + end process; + +end tb;