geoffrey/cdf2018-principal
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Motor controller via FPGA

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This commit is contained in:
Geoffrey Frogeye 2018-05-01 08:45:02 +02:00
parent 760b950e83
commit 4af0f8c865
21 changed files with 602 additions and 271 deletions
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2
fpga/Makefile
View file

@ -163,7 +163,7 @@ isimgui: build/isim_$(TB)$(EXE)
# Testing (using ghdl and gtkwave)
###########################################################################
GHDL_FLAGS=--mb-comments
GHDL_FLAGS=--mb-comments --ieee=synopsys
%_syntax: %.vhd
ghdl -s $(GHDL_FLAGS) "$<"

67
fpga/Principal.vhd
View file

@ -20,7 +20,13 @@ entity Principal is
FRONTTRIGGER: out std_logic;
FRONTECHO: in std_logic;
BACKTRIGGER: out std_logic;
BACKECHO: in std_logic
BACKECHO: in std_logic;
ENA: out std_logic;
IN1ENC: out std_logic;
IN2: out std_logic;
ENB: out std_logic;
IN3END: out std_logic;
IN4: out std_logic
);
end Principal;
@ -76,7 +82,22 @@ architecture Behavioral of Principal is
);
end component;
-- AF
-- Motor controller
signal enAd : std_logic_vector(7 downto 0);
signal in1enCd : std_logic_vector(7 downto 0);
signal in2d : std_logic;
signal enBd : std_logic_vector(7 downto 0);
signal in3enDd : std_logic_vector(7 downto 0);
signal in4d : std_logic;
component PWM is
port (
clk : in std_logic;
data : in std_logic_vector (7 downto 0);
pulse : out std_logic
);
end component;
-- CF
component uart is
generic (
baud : positive := fBaud;
@ -116,7 +137,13 @@ architecture Behavioral of Principal is
txStb : out std_logic;
txAck : in std_logic;
rxData : in std_logic_vector(7 downto 0);
rxStb : in std_logic
rxStb : in std_logic;
enA : out std_logic_vector(7 downto 0);
in1enC : out std_logic_vector(7 downto 0);
in2 : out std_logic;
enB : out std_logic_vector(7 downto 0);
in3enD : out std_logic_vector(7 downto 0);
in4 : out std_logic
);
end component;
@ -175,9 +202,33 @@ begin
signalIn => backRaw,
signalOut => back,
start => backFinished
-- done => done
-- done => done
);
enAp : PWM port map (
clk => CLK,
data => enAd,
pulse => ENA
);
in1enCp : PWM port map (
clk => CLK,
data => in1enCd,
pulse => IN1ENC
);
IN2 <= in2d;
enBp : PWM port map (
clk => CLK,
data => enBd,
pulse => ENB
);
in3enDp : PWM port map (
clk => CLK,
data => in3enDd,
pulse => IN3END
);
IN4 <= in4d;
FA: uart port map(
@ -204,7 +255,13 @@ begin
txStb => txStb,
txAck => txAck,
rxData => rxData,
rxStb => rxStb
rxStb => rxStb,
enA => enAd,
in1enC => in1enCd,
in2 => in2d,
enB => enBd,
in3enD => in3enDd,
in4 => in4d
);
end Behavioral;

48
fpga/Principal_tb.gtkw
View file

@ -1,20 +1,22 @@
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Tue Feb 27 18:30:48 2018
[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI
[*] Tue May 1 05:22:50 2018
[*]
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.ghw"
[dumpfile_mtime] "Tue Feb 27 18:29:45 2018"
[dumpfile_size] 4891772
[dumpfile_mtime] "Tue May 1 05:18:35 2018"
[dumpfile_size] 6534540
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/Principal_tb.gtkw"
[timestart] 0
[size] 1600 862
[pos] -1 -1
*-43.418156 1760000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-43.492355 11010000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.principal_tb.
[treeopen] top.principal_tb.dut.
[treeopen] top.principal_tb.dut.in1encp.
[treeopen] top.principal_tb.dut.in3endp.
[sst_width] 213
[signals_width] 198
[signals_width] 255
[sst_expanded] 1
[sst_vpaned_height] 296
@28
@ -95,11 +97,43 @@ top.principal_tb.dut.backcapt.start
top.principal_tb.dut.backcapt.trigger
[color] 3
top.principal_tb.dut.backcapt.echo
@8421
@8420
[color] 3
top.principal_tb.dut.backcapt.distancecounter
@420
[color] 3
top.principal_tb.dut.back
@22
[color] 5
#{top.principal_tb.dut.enad[7:0]} top.principal_tb.dut.enad[7] top.principal_tb.dut.enad[6] top.principal_tb.dut.enad[5] top.principal_tb.dut.enad[4] top.principal_tb.dut.enad[3] top.principal_tb.dut.enad[2] top.principal_tb.dut.enad[1] top.principal_tb.dut.enad[0]
@28
[color] 5
top.principal_tb.dut.ena
@22
[color] 5
#{top.principal_tb.dut.in1encd[7:0]} top.principal_tb.dut.in1encd[7] top.principal_tb.dut.in1encd[6] top.principal_tb.dut.in1encd[5] top.principal_tb.dut.in1encd[4] top.principal_tb.dut.in1encd[3] top.principal_tb.dut.in1encd[2] top.principal_tb.dut.in1encd[1] top.principal_tb.dut.in1encd[0]
@28
[color] 5
top.principal_tb.dut.in1enc
[color] 5
top.principal_tb.dut.in2d
[color] 5
top.principal_tb.dut.in2
@22
[color] 5
#{top.principal_tb.dut.enbd[7:0]} top.principal_tb.dut.enbd[7] top.principal_tb.dut.enbd[6] top.principal_tb.dut.enbd[5] top.principal_tb.dut.enbd[4] top.principal_tb.dut.enbd[3] top.principal_tb.dut.enbd[2] top.principal_tb.dut.enbd[1] top.principal_tb.dut.enbd[0]
@28
[color] 5
top.principal_tb.dut.enb
@22
[color] 5
#{top.principal_tb.dut.in3endd[7:0]} top.principal_tb.dut.in3endd[7] top.principal_tb.dut.in3endd[6] top.principal_tb.dut.in3endd[5] top.principal_tb.dut.in3endd[4] top.principal_tb.dut.in3endd[3] top.principal_tb.dut.in3endd[2] top.principal_tb.dut.in3endd[1] top.principal_tb.dut.in3endd[0]
@28
[color] 5
top.principal_tb.dut.in3end
[color] 5
top.principal_tb.dut.in4d
[color] 5
top.principal_tb.dut.in4
[pattern_trace] 1
[pattern_trace] 0

23
fpga/Principal_tb.vhd
View file

@ -30,7 +30,13 @@ architecture tb of Principal_tb is
FRONTTRIGGER: out std_logic;
FRONTECHO: in std_logic;
BACKTRIGGER: out std_logic;
BACKECHO: in std_logic
BACKECHO: in std_logic;
ENA: out std_logic;
IN1ENC: out std_logic;
IN2: out std_logic;
ENB: out std_logic;
IN3END: out std_logic;
IN4: out std_logic
);
end component;
@ -46,6 +52,12 @@ architecture tb of Principal_tb is
signal FRONTECHO : std_logic;
signal BACKTRIGGER : std_logic;
signal BACKECHO : std_logic;
signal ENA : std_logic;
signal IN1ENC : std_logic;
signal IN2 : std_logic;
signal ENB : std_logic;
signal IN3END : std_logic;
signal IN4 : std_logic;
constant TbPeriod : time := 500 ns;
signal TbClock : std_logic := '0';
@ -71,7 +83,14 @@ begin
FRONTTRIGGER => FRONTTRIGGER,
FRONTECHO => FRONTECHO,
BACKTRIGGER => BACKTRIGGER,
BACKECHO => BACKECHO);
BACKECHO => BACKECHO,
ENA => ENA,
IN1ENC => IN1ENC,
IN2 => IN2,
ENB => ENB,
IN3END => IN3END,
IN4 => IN4
);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

94
fpga/communication.vhd
View file

@ -16,31 +16,39 @@ entity communication is
txStb : out std_logic := '0';
txAck : in std_logic;
rxData : in std_logic_vector(7 downto 0);
rxStb : in std_logic
rxStb : in std_logic;
enA : out std_logic_vector(7 downto 0) := x"00";
in1enC : out std_logic_vector(7 downto 0) := x"00";
in2 : out std_logic := '0';
enB : out std_logic_vector(7 downto 0) := x"00";
in3enD : out std_logic_vector(7 downto 0) := x"00";
in4 : out std_logic := '0'
);
end communication;
architecture Behavioral of communication is
constant A2FD_PING : std_logic_vector(7 downto 0) := x"50"; -- 'P'
constant A2FD_RESETCODER : std_logic_vector(7 downto 0) := x"52"; -- 'R'
constant F2AD_ERR : std_logic_vector(7 downto 0) := x"45"; -- 'E'
constant C2FD_PING : std_logic_vector(7 downto 0) := x"50"; -- 'P'
constant C2FD_RESETCODER : std_logic_vector(7 downto 0) := x"52"; -- 'R'
constant F2CD_ERR : std_logic_vector(7 downto 0) := x"45"; -- 'E'
constant ERR_UNKNOWN_CODE : std_logic_vector(7 downto 0) := x"43"; -- 'C'
constant F2AI_CODER : std_logic_vector(7 downto 0) := x"44"; -- 'D'
constant F2AI_CAPT : std_logic_vector(7 downto 0) := x"43"; -- 'C'
constant F2AT_CAPT : std_logic_vector(7 downto 0) := x"63"; -- 'c'
constant F2CI_CODER : std_logic_vector(7 downto 0) := x"44"; -- 'D'
constant F2CI_CAPT : std_logic_vector(7 downto 0) := x"43"; -- 'C'
constant F2CT_CAPT : std_logic_vector(7 downto 0) := x"63"; -- 'c'
constant C2FD_PWM : std_logic_vector(7 downto 0) := x"57"; -- 'W'
constant C2FD_PWM2 : std_logic_vector(7 downto 0) := x"77"; -- 'w'
signal frontTrigger : integer := 0;
signal backTrigger : integer := 0;
signal triggerSet : std_logic := '0';
type readMessages is (F2AT_CAPTs);
type readMessages is (F2CT_CAPTs, C2FD_PWMs, C2FD_PWM2s);
signal readMessage : readMessages;
signal readSize : integer := 0;
signal readOffset : integer := 0;
signal readData : std_logic_vector(63 downto 0) := (others => '0'); -- Max message size (will be trimmed down by the synthetizer)
type sendMessages is (A2FD_PINGs, F2AI_CODERs, F2AI_CAPTs, F2AD_ERR_UNKNOWN_CODEs);
type sendMessages is (C2FD_PINGs, F2CI_CODERs, F2CI_CAPTs, F2CD_ERR_UNKNOWN_CODEs);
constant SENDQUEUE_SIZE : integer := 16;
type sendQueueMemorya is array (0 to SENDQUEUE_SIZE - 1) of sendMessages;
signal sendQueueMemory : sendQueueMemorya;
@ -98,17 +106,23 @@ begin
if readSize = 0 then -- Beginning of message
readSize <= 0;
case rxData is
when A2FD_PING =>
pushSend(A2FD_PINGs);
when F2AI_CODER =>
pushSend(F2AI_CODERs);
when F2AI_CAPT =>
pushSend(F2AI_CAPTs);
when F2AT_CAPT =>
readMessage <= F2AT_CAPTs;
when C2FD_PING =>
pushSend(C2FD_PINGs);
when F2CI_CODER =>
pushSend(F2CI_CODERs);
when F2CI_CAPT =>
pushSend(F2CI_CAPTs);
when F2CT_CAPT =>
readMessage <= F2CT_CAPTs;
readSize <= 4;
when C2FD_PWM =>
readMessage <= C2FD_PWMs;
readSize <= 3;
when C2FD_PWM2 =>
readMessage <= C2FD_PWM2s;
readSize <= 4;
when others =>
pushSend(F2AD_ERR_UNKNOWN_CODEs);
pushSend(F2CD_ERR_UNKNOWN_CODEs);
end case;
else -- Rest of message
if readOffset < readSize then
@ -118,17 +132,39 @@ begin
end if;
elsif readSize > 0 and readOffset = readSize then -- Rest of message ended
case readMessage is
when F2AT_CAPTs =>
when F2CT_CAPTs =>
frontTrigger <= to_integer(unsigned(readData(15 downto 0)));
backTrigger <= to_integer(unsigned(readData(31 downto 16)));
triggerSet <= '1';
when C2FD_PWMs =>
enA <= readData(7 downto 0);
enB <= readData(15 downto 8);
if readData(16) = '1' then
in1enC <= x"FF";
else
in1enC <= x"00";
end if;
in2 <= readData(17);
if readData(18) = '1' then
in3enD <= x"FF";
else
in3enD <= x"00";
end if;
in4 <= readData(19);
when C2FD_PWM2s =>
enA <= readData(7 downto 0);
in1enC <= readData(15 downto 8);
enB <= readData(23 downto 16);
in3enD <= readData(31 downto 24);
in2 <= '0';
in4 <= '0';
when others =>
pushSend(F2AD_ERR_UNKNOWN_CODEs);
pushSend(F2CD_ERR_UNKNOWN_CODEs);
end case;
readOffset <= 0;
readSize <= 0;
elsif (triggerSet = '1' and ((front > frontTrigger) or (back > backTrigger))) then
pushSend(F2AI_CAPTs);
pushSend(F2CI_CAPTs);
triggerSet <= '0';
end if;
@ -146,22 +182,22 @@ begin
sendAvailable <= '1';
case sendQueueMemory(sendTail) is
when A2FD_PINGs =>
sendData(7 downto 0) <= A2FD_PING;
when C2FD_PINGs =>
sendData(7 downto 0) <= C2FD_PING;
sendSize <= 1;
when F2AI_CAPTs =>
sendData(7 downto 0) <= F2AI_CAPT;
when F2CI_CAPTs =>
sendData(7 downto 0) <= F2CI_CAPT;
sendData(23 downto 8) <= std_logic_vector(to_signed(front, 16));
sendData(39 downto 24) <= std_logic_vector(to_unsigned(back, 16));
sendSize <= 5;
when F2AI_CODERs =>
when F2CI_CODERs =>
zerocoder <= '1';
sendData(7 downto 0) <= F2AI_CODER;
sendData(7 downto 0) <= F2CI_CODER;
sendData(23 downto 8) <= std_logic_vector(to_signed(left, 16));
sendData(39 downto 24) <= std_logic_vector(to_signed(right, 16));
sendSize <= 5;
when others => -- Including F2AD_ERR_UNKNOWN_CODEs
sendData(7 downto 0) <= F2AD_ERR;
when others => -- Including F2CD_ERR_UNKNOWN_CODEs
sendData(7 downto 0) <= F2CD_ERR;
sendData(15 downto 8) <= ERR_UNKNOWN_CODE;
sendSize <= 2;
end case;

27
fpga/communication_tb.gtkw
View file

@ -1,15 +1,15 @@
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Wed Feb 28 14:53:10 2018
[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI
[*] Tue May 1 04:06:11 2018
[*]
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/communication_tb.ghw"
[dumpfile_mtime] "Wed Feb 28 14:51:41 2018"
[dumpfile_size] 7845
[dumpfile_mtime] "Tue May 1 04:02:41 2018"
[dumpfile_size] 8903
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/communication_tb.gtkw"
[timestart] 0
[size] 1600 862
[pos] -1 -1
*-30.009827 1783000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-30.189280 1783000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.communication_tb.
[treeopen] top.communication_tb.dut.
@ -66,5 +66,22 @@ top.communication_tb.dut.backtrigger
top.communication_tb.dut.front
[color] 2
top.communication_tb.dut.back
@22
[color] 6
#{top.communication_tb.ena[7:0]} top.communication_tb.ena[7] top.communication_tb.ena[6] top.communication_tb.ena[5] top.communication_tb.ena[4] top.communication_tb.ena[3] top.communication_tb.ena[2] top.communication_tb.ena[1] top.communication_tb.ena[0]
[color] 6
#{top.communication_tb.in1enc[7:0]} top.communication_tb.in1enc[7] top.communication_tb.in1enc[6] top.communication_tb.in1enc[5] top.communication_tb.in1enc[4] top.communication_tb.in1enc[3] top.communication_tb.in1enc[2] top.communication_tb.in1enc[1] top.communication_tb.in1enc[0]
@28
[color] 6
top.communication_tb.dut.in2
@22
[color] 6
#{top.communication_tb.enb[7:0]} top.communication_tb.enb[7] top.communication_tb.enb[6] top.communication_tb.enb[5] top.communication_tb.enb[4] top.communication_tb.enb[3] top.communication_tb.enb[2] top.communication_tb.enb[1] top.communication_tb.enb[0]
@80023
[color] 6
#{top.communication_tb.in3end[7:0]} top.communication_tb.in3end[7] top.communication_tb.in3end[6] top.communication_tb.in3end[5] top.communication_tb.in3end[4] top.communication_tb.in3end[3] top.communication_tb.in3end[2] top.communication_tb.in3end[1] top.communication_tb.in3end[0]
@28
[color] 6
top.communication_tb.dut.in4
[pattern_trace] 1
[pattern_trace] 0

64
fpga/communication_tb.vhd
View file

@ -23,7 +23,14 @@ architecture tb of communication_tb is
txStb : out std_logic;
txAck : in std_logic;
rxData : in std_logic_vector (7 downto 0);
rxStb : in std_logic);
rxStb : in std_logic;
enA : out std_logic_vector(7 downto 0);
in1enC : out std_logic_vector(7 downto 0);
in2 : out std_logic;
enB : out std_logic_vector(7 downto 0);
in3enD : out std_logic_vector(7 downto 0);
in4 : out std_logic
);
end component;
signal clock : std_logic;
@ -38,6 +45,12 @@ architecture tb of communication_tb is
signal txAck : std_logic;
signal rxData : std_logic_vector (7 downto 0);
signal rxStb : std_logic;
signal enA : std_logic_vector(7 downto 0);
signal in1enC : std_logic_vector(7 downto 0);
signal in2 : std_logic;
signal enB : std_logic_vector(7 downto 0);
signal in3enD : std_logic_vector(7 downto 0);
signal in4 : std_logic;
constant TbPeriod : time := 20 ns;
signal TbClock : std_logic := '0';
@ -59,7 +72,14 @@ begin
zerocoder => zerocoder,
txAck => txAck,
rxData => rxData,
rxStb => rxStb);
rxStb => rxStb,
enA => enA,
in1enC => in1enC,
in2 => in2,
enB => enB,
in3enD => in3enD,
in4 => in4
);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
@ -245,6 +265,46 @@ begin
wait for 100 ns;
-- Test PWM1
report "TEST Receiving 'W'" severity note;
tampon(0 to 3) := (x"57", x"CC", x"77", x"03");
for I in 0 to 3 loop
rxData <= tampon(I);
rxStb <= '1';
wait for TbPeriod;
rxStb <= '0';
wait for TbPeriod;
end loop;
assert enA = x"CC" report "ENA not at correct value" severity error;
assert enB = x"77" report "ENB not at correct value" severity error;
assert in1enC = x"FF" report "IN1 not at correct value" severity error;
assert in2 = '1' report "IN1 not at correct value" severity error;
assert in3enD = x"00" report "IN3 not at correct value" severity error;
assert in4 = '0' report "IN4 not at correct value" severity error;
wait for 100 ns;
-- Test PWM2
report "TEST Receiving 'w'" severity note;
tampon(0 to 4) := (x"77", x"11", x"22", x"33", x"44");
for I in 0 to 4 loop
rxData <= tampon(I);
rxStb <= '1';
wait for TbPeriod;
rxStb <= '0';
wait for TbPeriod;
end loop;
assert enA = x"11" report "ENA not at correct value" severity error;
assert in1enC = x"22" report "ENC not at correct value" severity error;
assert enB = x"33" report "ENB not at correct value" severity error;
assert in3enD = x"44" report "END not at correct value" severity error;
wait for 100 ns;
TbSimEnded <= '1';
wait;

64
fpga/principal.ucf
View file

@ -7,32 +7,56 @@ TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
# BTN
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
# IO<0>
NET "RX" LOC = "P59" | IOSTANDARD = LVTTL ;
# IO<10>
NET "RX" LOC = "P85" | IOSTANDARD = LVTTL ;
# IO<1>
NET "TX" LOC = "P60" | IOSTANDARD = LVTTL ;
# IO<11>
NET "TX" LOC = "P84" | IOSTANDARD = LVTTL ;
# IO<2>
NET "LEFTCHA" LOC = "P61" | IOSTANDARD = LVTTL ;
# IO<12>
NET "LEFTCHA" LOC = "P83" | IOSTANDARD = LVTTL ;
# IO<3>
NET "LEFTCHB" LOC = "P62" | IOSTANDARD = LVTTL ;
# IO<13>
NET "LEFTCHB" LOC = "P78" | IOSTANDARD = LVTTL ;
# IO<4>
NET "RIGHTCHA" LOC = "P64" | IOSTANDARD = LVTTL ;
# IO<14>
NET "RIGHTCHA" LOC = "P77" | IOSTANDARD = LVTTL ;
# IO<5>
NET "RIGHTCHB" LOC = "P57" | IOSTANDARD = LVTTL ;
# IO<15>
NET "RIGHTCHB" LOC = "P65" | IOSTANDARD = LVTTL ;
# IO<6>
NET "FRONTTRIGGER" LOC = "P56" | IOSTANDARD = LVTTL ;
# IO<16>
NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ;
# IO<7>
NET "FRONTECHO" LOC = "P52" | IOSTANDARD = LVTTL ;
# IO<17>
NET "FRONTECHO" LOC = "P71" | IOSTANDARD = LVTTL ;
# IO<8>
NET "BACKTRIGGER" LOC = "P50" | IOSTANDARD = LVTTL ;
# IO<18>
NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ;
# IO<9>
NET "BACKECHO" LOC = "P49" | IOSTANDARD = LVTTL ;
# IO<19>
NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ;
# IO<20>
NET "ENA" LOC = "P5" | IOSTANDARD = LVTTL ;
# IO<21>
NET "IN1ENC" LOC = "P4" | IOSTANDARD = LVTTL ;
# IO<22>
NET "IN2" LOC = "P6" | IOSTANDARD = LVTTL ;
# IO<23>
NET "ENB" LOC = "P98" | IOSTANDARD = LVTTL ;
# IO<24>
NET "IN3END" LOC = "P94" | IOSTANDARD = LVTTL ;
# IO<25>
NET "IN4" LOC = "P93" | IOSTANDARD = LVTTL ;
# NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
# NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
# NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
# NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;

2
fpga/project.cfg
View file

@ -5,5 +5,5 @@ PROGRAMMER = mercpcl
TOPLEVEL = Principal
# Prod
VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd fir.vhd
VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd fir.vhd pwm.vhd
CONSTRAINTS = principal.ucf

30
fpga/pwm.vhd Normal file
View file

@ -0,0 +1,30 @@
-- Inspiré de http://www.fpga4fun.com/PWM_DAC_2.html
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity PWM is
port (
clk : in std_logic;
data : in std_logic_vector (7 downto 0) := "00000000";
pulse : out std_logic
);
end PWM;
architecture Behavioral of PWM is
signal accuI : integer;
signal dataI : integer;
begin
dataI <= to_integer(unsigned(data));
process(clk, data)
begin
if rising_edge(clk) then
accuI <= accuI mod 256 + dataI + 1;
end if;
end process;
pulse <= '1' when accuI >= 256 else '0';
end Behavioral;