From 5c1ccbce93c32bc735afafd9846d2c0640ed16df Mon Sep 17 00:00:00 2001
From: Geoffrey Frogeye <geoffrey@frogeye.fr>
Date: Fri, 2 Mar 2018 15:01:48 +0100
Subject: [PATCH] =?UTF-8?q?FPGA=20:=20Suppression=20d=C3=A9lai=20inutile?=
 =?UTF-8?q?=20encodeurs?=
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---
 fpga/hedm.vhd    | 28 +++++++++++-----------------
 fpga/hedm_tb.vhd |  2 +-
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/fpga/hedm.vhd b/fpga/hedm.vhd
index a54ecf5..556ce4f 100644
--- a/fpga/hedm.vhd
+++ b/fpga/hedm.vhd
@@ -20,7 +20,6 @@ entity hedm is
 end hedm;
 
 architecture Behavioral of hedm is
-    signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
     signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
 begin
     processInput : process(clk, reset)
@@ -29,18 +28,10 @@ begin
         if reset = '1' then
             counter := 0;
             counts <= 0;
-            An <= '0';
-            Bn <= '0';
             Ap <= '0';
             Bp <= '0';
         elsif rising_edge(clk) then
 
-            Ap <= An;
-            Bp <= Bn;
-
-            An <= chA;
-            Bn <= chB;
-
             if zero = '1' then
                 counter := 0;
             end if;
@@ -49,32 +40,35 @@ begin
             -- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
             -- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
 
-            if (Ap = '0' and An = '1') then -- Front montant A
-                if (Bn = '0') then
+            if (Ap = '0' and chA = '1') then -- Front montant A
+                if (chB = '0') then
                     counter := counter + 1;
                 else
                     counter := counter - 1;
                 end if;
-            elsif (Ap = '1' and An = '0') then -- Front descendant A
-                if (Bn = '1') then
+            elsif (Ap = '1' and chA = '0') then -- Front descendant A
+                if (chB = '1') then
                     counter := counter + 1;
                 else
                     counter := counter - 1;
                 end if;
-            elsif (Bp = '0' and Bn = '1') then -- Front montant B
-                if (An = '1') then
+            elsif (Bp = '0' and chB = '1') then -- Front montant B
+                if (chA = '1') then
                     counter := counter + 1;
                 else
                     counter := counter - 1;
                 end if;
-            elsif (Bp = '1' and Bn = '0') then -- Front descendant B
-                if (An = '0') then
+            elsif (Bp = '1' and chB = '0') then -- Front descendant B
+                if (chA = '0') then
                     counter := counter + 1;
                 else
                     counter := counter - 1;
                 end if;
             end if;
 
+            Ap <= chA;
+            Bp <= chB;
+
             counts <= counter;
 
         end if;
diff --git a/fpga/hedm_tb.vhd b/fpga/hedm_tb.vhd
index 25714c7..cb917b4 100644
--- a/fpga/hedm_tb.vhd
+++ b/fpga/hedm_tb.vhd
@@ -112,7 +112,7 @@ begin
         wait for TbPeriod;
 
         wait for 5 * TbPeriod;
-        assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
+        assert counts = 2 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
 
         zero <= '1';
         wait for TbPeriod;