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FPGA : Nettoyage des modules de debug

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Geoffrey Frogeye 2018-03-02 14:30:00 +01:00
parent 6013d6c9a9
commit 6082662c2d
4 changed files with 0 additions and 259 deletions
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90
fpga/mercury.ucf
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# __ ____ _ __
# / |/ (_)_____________ / | / /___ _ ______ _
# / /|_/ / / ___/ ___/ __ \/ |/ / __ \ | / / __ `/
# / / / / / /__/ / / /_/ / /| / /_/ / |/ / /_/ /
# /_/ /_/_/\___/_/ \____/_/ |_/\____/|___/\__,_/
#
# Mercury User Constraints File
# Revision 1.0.142 (10/24/2012)
# Copyright (c) 2012 MicroNova, LLC
# www.micro-nova.com
# system oscillator
NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
# user LEDs and button
NET "LED<0>" LOC = "P13" | IOSTANDARD = LVTTL ;
NET "LED<1>" LOC = "P15" | IOSTANDARD = LVTTL ;
NET "LED<2>" LOC = "P16" | IOSTANDARD = LVTTL ;
NET "LED<3>" LOC = "P19" | IOSTANDARD = LVTTL ;
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
# direct and global-clock I/O
NET "DIO<0>" LOC = "P20" | IOSTANDARD = LVTTL ;
NET "DIO<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
NET "DIO<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
NET "DIO<3>" LOC = "P34" | IOSTANDARD = LVTTL ;
NET "DIO<4>" LOC = "P35" | IOSTANDARD = LVTTL ;
NET "DIO<5>" LOC = "P36" | IOSTANDARD = LVTTL ;
NET "DIO<6>" LOC = "P37" | IOSTANDARD = LVTTL ;
NET "CIO<0>" LOC = "P40" | IOSTANDARD = LVTTL ;
NET "CIO<1>" LOC = "P44" | IOSTANDARD = LVTTL ;
# in-only pins
NET "INPIN<0>" LOC = "P68" | IOSTANDARD = LVTTL ;
NET "INPIN<1>" LOC = "P97" | IOSTANDARD = LVTTL ;
NET "INPIN<2>" LOC = "P7" | IOSTANDARD = LVTTL ;
NET "INPIN<3>" LOC = "P82" | IOSTANDARD = LVTTL ;
# level-shifted I/O
NET "IO<0>" LOC = "P59" | IOSTANDARD = LVTTL ;
NET "IO<1>" LOC = "P60" | IOSTANDARD = LVTTL ;
NET "IO<2>" LOC = "P61" | IOSTANDARD = LVTTL ;
NET "IO<3>" LOC = "P62" | IOSTANDARD = LVTTL ;
NET "IO<4>" LOC = "P64" | IOSTANDARD = LVTTL ;
NET "IO<5>" LOC = "P57" | IOSTANDARD = LVTTL ;
NET "IO<6>" LOC = "P56" | IOSTANDARD = LVTTL ;
NET "IO<7>" LOC = "P52" | IOSTANDARD = LVTTL ;
NET "IO<8>" LOC = "P50" | IOSTANDARD = LVTTL ;
NET "IO<9>" LOC = "P49" | IOSTANDARD = LVTTL ;
NET "IO<10>" LOC = "P85" | IOSTANDARD = LVTTL ;
NET "IO<11>" LOC = "P84" | IOSTANDARD = LVTTL ;
NET "IO<12>" LOC = "P83" | IOSTANDARD = LVTTL ;
NET "IO<13>" LOC = "P78" | IOSTANDARD = LVTTL ;
NET "IO<14>" LOC = "P77" | IOSTANDARD = LVTTL ;
NET "IO<15>" LOC = "P65" | IOSTANDARD = LVTTL ;
NET "IO<16>" LOC = "P70" | IOSTANDARD = LVTTL ;
NET "IO<17>" LOC = "P71" | IOSTANDARD = LVTTL ;
NET "IO<18>" LOC = "P72" | IOSTANDARD = LVTTL ;
NET "IO<19>" LOC = "P73" | IOSTANDARD = LVTTL ;
NET "IO<20>" LOC = "P5" | IOSTANDARD = LVTTL ;
NET "IO<21>" LOC = "P4" | IOSTANDARD = LVTTL ;
NET "IO<22>" LOC = "P6" | IOSTANDARD = LVTTL ;
NET "IO<23>" LOC = "P98" | IOSTANDARD = LVTTL ;
NET "IO<24>" LOC = "P94" | IOSTANDARD = LVTTL ;
NET "IO<25>" LOC = "P93" | IOSTANDARD = LVTTL ;
NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;
# memory & bus-switch
NET "switch_oen" LOC = "P3" | IOSTANDARD = LVTTL ;
NET "memory_oen" LOC = "P30" | IOSTANDARD = LVTTL ;
# flash/usb interface
NET "fpga_csn" LOC = "P39" | IOSTANDARD = LVTTL ;
NET "flash_csn" LOC = "P27" | IOSTANDARD = LVTTL ;
NET "spi_mosi" LOC = "P46" | IOSTANDARD = LVTTL ;
NET "spi_miso" LOC = "P51" | IOSTANDARD = LVTTL ;
NET "spi_sck" LOC = "P53" | IOSTANDARD = LVTTL ;
# ADC interface
NET "adc_miso" LOC = "P21" | IOSTANDARD = LVTTL ;
NET "adc_mosi" LOC = "P10" | IOSTANDARD = LVTTL ;
NET "adc_sck" LOC = "P9" | IOSTANDARD = LVTTL ;
NET "adc_csn" LOC = "P12" | IOSTANDARD = LVTTL ;
# CLOCK timing

72
fpga/sevenseg.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sevenseg is
Port (
data : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
anode : out STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (6 downto 0);
dot : out STD_LOGIC
);
end sevenseg;
architecture structural of sevenseg is
signal digit: std_logic_vector(3 downto 0);
signal selector: integer := 0;
signal counter : integer := 0;
begin
with selector select
anode <= "1110" when 0,
"1101" when 1,
"1011" when 2,
"0111" when 3,
"0000" when others;
with selector select
digit <= data(3 downto 0) when 0,
data(7 downto 4) when 1,
data(11 downto 8) when 2,
data(15 downto 12) when 3,
"0000" when others;
with digit select
segment <= "0000001" when "0000", -- 0
"1001111" when "0001", -- 1
"0010010" when "0010", -- 2
"0000110" when "0011", -- 3
"1001100" when "0100", -- 4
"0100100" when "0101", -- 5
"0100000" when "0110", -- 6
"0001111" when "0111", -- 7
"0000000" when "1000", -- 8
"0000100" when "1001", -- 9
"0001000" when "1010", -- A
"1100000" when "1011", -- b
"0110001" when "1100", -- C
"1000010" when "1101", -- d
"0110000" when "1110", -- E
"0111000" when "1111", -- F
"0000000" when others;
dot <= '1';
alternateur : process(clock)
begin
if clock'event and clock = '1' then
counter <= counter + 1;
if counter >= 199999 then
selector <= selector + 1;
if selector >= 3 then
selector <= 0;
end if;
counter <= 0;
end if;
end if;
end process;
end structural;

38
fpga/sevenseg_tb.gtkw
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[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Sun Feb 25 12:47:52 2018
[*]
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/sevenseg_tb.vcd"
[dumpfile_mtime] "Sun Feb 25 12:44:56 2018"
[dumpfile_size] 111992791
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/sevenseg_tb.gtkw"
[timestart] 0
[size] 1680 1012
[pos] -1 -1
*-42.000000 2550000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 213
[signals_width] 126
[sst_expanded] 1
[sst_vpaned_height] 296
@23
dut.data[15:0]
@28
dut.clock
@8420
[color] 2
dut.counter
@420
[color] 2
dut.selector
@22
[color] 2
dut.digit[3:0]
[color] 1
dut.anode[3:0]
@28
[color] 1
dut.segment[6:0]
[color] 1
dut.dot
[pattern_trace] 1
[pattern_trace] 0

59
fpga/sevenseg_tb.vhd
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-- Testbench automatically generated online
-- at http://vhdl.lapinoo.net
-- Generation date : 25.2.2018 12:42:48 GMT
library ieee;
use ieee.std_logic_1164.all;
entity sevenseg_tb is
end sevenseg_tb;
architecture tb of sevenseg_tb is
component sevenseg
port (data : in std_logic_vector (15 downto 0);
clock : in std_logic;
anode : out std_logic_vector (3 downto 0);
segment : out std_logic_vector (6 downto 0);
dot : out std_logic);
end component;
signal data : std_logic_vector (15 downto 0);
signal clock : std_logic;
signal anode : std_logic_vector (3 downto 0);
signal segment : std_logic_vector (6 downto 0);
signal dot : std_logic;
constant TbPeriod : time := 20 ns;
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
constant SegPeriod : time := 4 ms;
constant FourSegPeriod : time := 4 * SegPeriod;
begin
dut : sevenseg
port map (data => data,
clock => clock,
anode => anode,
segment => segment,
dot => dot);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
clock <= TbClock;
stimuli : process
begin
data <= x"0123";
wait for 2 * FourSegPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
wait;
end process;
end tb;