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FPGA : Nettoyage des modules de debug
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# __ ____ _ __
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# / |/ (_)_____________ / | / /___ _ ______ _
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# / /|_/ / / ___/ ___/ __ \/ |/ / __ \ | / / __ `/
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# / / / / / /__/ / / /_/ / /| / /_/ / |/ / /_/ /
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# /_/ /_/_/\___/_/ \____/_/ |_/\____/|___/\__,_/
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#
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# Mercury User Constraints File
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# Revision 1.0.142 (10/24/2012)
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# Copyright (c) 2012 MicroNova, LLC
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# www.micro-nova.com
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# system oscillator
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NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
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NET "CLK" TNM_NET = "CLK";
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TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
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# user LEDs and button
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NET "LED<0>" LOC = "P13" | IOSTANDARD = LVTTL ;
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NET "LED<1>" LOC = "P15" | IOSTANDARD = LVTTL ;
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NET "LED<2>" LOC = "P16" | IOSTANDARD = LVTTL ;
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NET "LED<3>" LOC = "P19" | IOSTANDARD = LVTTL ;
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NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
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# direct and global-clock I/O
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NET "DIO<0>" LOC = "P20" | IOSTANDARD = LVTTL ;
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NET "DIO<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
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NET "DIO<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
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NET "DIO<3>" LOC = "P34" | IOSTANDARD = LVTTL ;
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NET "DIO<4>" LOC = "P35" | IOSTANDARD = LVTTL ;
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NET "DIO<5>" LOC = "P36" | IOSTANDARD = LVTTL ;
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NET "DIO<6>" LOC = "P37" | IOSTANDARD = LVTTL ;
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NET "CIO<0>" LOC = "P40" | IOSTANDARD = LVTTL ;
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NET "CIO<1>" LOC = "P44" | IOSTANDARD = LVTTL ;
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# in-only pins
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NET "INPIN<0>" LOC = "P68" | IOSTANDARD = LVTTL ;
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NET "INPIN<1>" LOC = "P97" | IOSTANDARD = LVTTL ;
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NET "INPIN<2>" LOC = "P7" | IOSTANDARD = LVTTL ;
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NET "INPIN<3>" LOC = "P82" | IOSTANDARD = LVTTL ;
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# level-shifted I/O
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NET "IO<0>" LOC = "P59" | IOSTANDARD = LVTTL ;
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NET "IO<1>" LOC = "P60" | IOSTANDARD = LVTTL ;
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NET "IO<2>" LOC = "P61" | IOSTANDARD = LVTTL ;
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NET "IO<3>" LOC = "P62" | IOSTANDARD = LVTTL ;
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NET "IO<4>" LOC = "P64" | IOSTANDARD = LVTTL ;
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NET "IO<5>" LOC = "P57" | IOSTANDARD = LVTTL ;
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NET "IO<6>" LOC = "P56" | IOSTANDARD = LVTTL ;
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NET "IO<7>" LOC = "P52" | IOSTANDARD = LVTTL ;
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NET "IO<8>" LOC = "P50" | IOSTANDARD = LVTTL ;
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NET "IO<9>" LOC = "P49" | IOSTANDARD = LVTTL ;
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NET "IO<10>" LOC = "P85" | IOSTANDARD = LVTTL ;
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NET "IO<11>" LOC = "P84" | IOSTANDARD = LVTTL ;
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NET "IO<12>" LOC = "P83" | IOSTANDARD = LVTTL ;
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NET "IO<13>" LOC = "P78" | IOSTANDARD = LVTTL ;
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NET "IO<14>" LOC = "P77" | IOSTANDARD = LVTTL ;
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NET "IO<15>" LOC = "P65" | IOSTANDARD = LVTTL ;
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NET "IO<16>" LOC = "P70" | IOSTANDARD = LVTTL ;
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NET "IO<17>" LOC = "P71" | IOSTANDARD = LVTTL ;
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NET "IO<18>" LOC = "P72" | IOSTANDARD = LVTTL ;
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NET "IO<19>" LOC = "P73" | IOSTANDARD = LVTTL ;
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NET "IO<20>" LOC = "P5" | IOSTANDARD = LVTTL ;
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NET "IO<21>" LOC = "P4" | IOSTANDARD = LVTTL ;
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NET "IO<22>" LOC = "P6" | IOSTANDARD = LVTTL ;
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NET "IO<23>" LOC = "P98" | IOSTANDARD = LVTTL ;
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NET "IO<24>" LOC = "P94" | IOSTANDARD = LVTTL ;
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NET "IO<25>" LOC = "P93" | IOSTANDARD = LVTTL ;
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NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
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NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
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NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
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NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;
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# memory & bus-switch
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NET "switch_oen" LOC = "P3" | IOSTANDARD = LVTTL ;
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NET "memory_oen" LOC = "P30" | IOSTANDARD = LVTTL ;
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# flash/usb interface
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NET "fpga_csn" LOC = "P39" | IOSTANDARD = LVTTL ;
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NET "flash_csn" LOC = "P27" | IOSTANDARD = LVTTL ;
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NET "spi_mosi" LOC = "P46" | IOSTANDARD = LVTTL ;
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NET "spi_miso" LOC = "P51" | IOSTANDARD = LVTTL ;
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NET "spi_sck" LOC = "P53" | IOSTANDARD = LVTTL ;
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# ADC interface
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NET "adc_miso" LOC = "P21" | IOSTANDARD = LVTTL ;
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NET "adc_mosi" LOC = "P10" | IOSTANDARD = LVTTL ;
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NET "adc_sck" LOC = "P9" | IOSTANDARD = LVTTL ;
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NET "adc_csn" LOC = "P12" | IOSTANDARD = LVTTL ;
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# CLOCK timing
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@ -1,72 +0,0 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity sevenseg is
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Port (
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data : in STD_LOGIC_VECTOR (15 downto 0);
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clock : in STD_LOGIC;
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anode : out STD_LOGIC_VECTOR (3 downto 0);
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segment : out STD_LOGIC_VECTOR (6 downto 0);
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dot : out STD_LOGIC
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);
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end sevenseg;
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architecture structural of sevenseg is
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signal digit: std_logic_vector(3 downto 0);
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signal selector: integer := 0;
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signal counter : integer := 0;
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begin
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with selector select
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anode <= "1110" when 0,
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"1101" when 1,
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"1011" when 2,
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"0111" when 3,
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"0000" when others;
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with selector select
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digit <= data(3 downto 0) when 0,
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data(7 downto 4) when 1,
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data(11 downto 8) when 2,
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data(15 downto 12) when 3,
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"0000" when others;
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with digit select
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segment <= "0000001" when "0000", -- 0
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"1001111" when "0001", -- 1
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"0010010" when "0010", -- 2
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"0000110" when "0011", -- 3
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"1001100" when "0100", -- 4
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"0100100" when "0101", -- 5
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"0100000" when "0110", -- 6
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"0001111" when "0111", -- 7
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"0000000" when "1000", -- 8
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"0000100" when "1001", -- 9
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"0001000" when "1010", -- A
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"1100000" when "1011", -- b
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"0110001" when "1100", -- C
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"1000010" when "1101", -- d
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"0110000" when "1110", -- E
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"0111000" when "1111", -- F
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"0000000" when others;
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dot <= '1';
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alternateur : process(clock)
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begin
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if clock'event and clock = '1' then
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counter <= counter + 1;
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if counter >= 199999 then
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selector <= selector + 1;
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if selector >= 3 then
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selector <= 0;
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end if;
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counter <= 0;
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end if;
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end if;
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end process;
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end structural;
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@ -1,38 +0,0 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Sun Feb 25 12:47:52 2018
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[*]
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[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/sevenseg_tb.vcd"
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[dumpfile_mtime] "Sun Feb 25 12:44:56 2018"
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[dumpfile_size] 111992791
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[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/sevenseg_tb.gtkw"
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[timestart] 0
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[size] 1680 1012
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[pos] -1 -1
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*-42.000000 2550000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 213
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[signals_width] 126
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[sst_expanded] 1
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[sst_vpaned_height] 296
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@23
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dut.data[15:0]
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@28
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dut.clock
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@8420
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[color] 2
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dut.counter
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@420
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[color] 2
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dut.selector
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@22
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[color] 2
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dut.digit[3:0]
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[color] 1
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dut.anode[3:0]
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@28
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[color] 1
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dut.segment[6:0]
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[color] 1
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dut.dot
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[pattern_trace] 1
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[pattern_trace] 0
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@ -1,59 +0,0 @@
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-- Testbench automatically generated online
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-- at http://vhdl.lapinoo.net
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-- Generation date : 25.2.2018 12:42:48 GMT
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library ieee;
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use ieee.std_logic_1164.all;
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entity sevenseg_tb is
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end sevenseg_tb;
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architecture tb of sevenseg_tb is
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component sevenseg
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port (data : in std_logic_vector (15 downto 0);
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clock : in std_logic;
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anode : out std_logic_vector (3 downto 0);
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segment : out std_logic_vector (6 downto 0);
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dot : out std_logic);
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end component;
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signal data : std_logic_vector (15 downto 0);
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signal clock : std_logic;
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signal anode : std_logic_vector (3 downto 0);
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signal segment : std_logic_vector (6 downto 0);
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signal dot : std_logic;
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constant TbPeriod : time := 20 ns;
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signal TbClock : std_logic := '0';
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signal TbSimEnded : std_logic := '0';
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constant SegPeriod : time := 4 ms;
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constant FourSegPeriod : time := 4 * SegPeriod;
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begin
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dut : sevenseg
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port map (data => data,
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clock => clock,
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anode => anode,
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segment => segment,
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dot => dot);
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-- Clock generation
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TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
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clock <= TbClock;
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stimuli : process
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begin
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data <= x"0123";
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wait for 2 * FourSegPeriod;
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-- Stop the clock and hence terminate the simulation
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TbSimEnded <= '1';
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wait;
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end process;
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end tb;
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