From 9a2bf3d9cd845a4d7b52ebed961e47346d73c8d5 Mon Sep 17 00:00:00 2001 From: Geoffrey Frogeye Date: Sun, 25 Feb 2018 13:49:53 +0100 Subject: [PATCH] =?UTF-8?q?FPGA=20:=20Am=C3=A9lioration=20code=207-segment?= =?UTF-8?q?s?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- fpga/Makefile | 2 +- fpga/sevenseg.vhd | 14 ++++++---- fpga/sevenseg_tb.gtkw | 38 ++++++++++++++++++++++++++++ fpga/sevenseg_tb.vhd | 59 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 107 insertions(+), 6 deletions(-) create mode 100644 fpga/sevenseg_tb.gtkw create mode 100644 fpga/sevenseg_tb.vhd diff --git a/fpga/Makefile b/fpga/Makefile index 3614648..bb32954 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -170,7 +170,7 @@ build/%.o: %.vhd ghdl -a --mb-comments --workdir="$(shell dirname "$@")" "$<" build/%_tb: build/%_tb.o $(addprefix build/,$(subst .vhd,.o,$(VHDSOURCE))) - ghdl -e --workdir="$(shell dirname "$@")" -o "$@" "$(basename $(notdir $<))" + ghdl -e --workdir="$(shell dirname "$@")" -o "$(shell echo "$@" | tr A-Z a-z)" "$(basename $(notdir $<))" build/%_tb.vcd: build/%_tb (cd "$(shell dirname "$<")"; ghdl -r "$(basename $(notdir $<))" --vcd="../$@" ) diff --git a/fpga/sevenseg.vhd b/fpga/sevenseg.vhd index c10b2d9..a133db6 100644 --- a/fpga/sevenseg.vhd +++ b/fpga/sevenseg.vhd @@ -14,8 +14,8 @@ end sevenseg; architecture structural of sevenseg is signal digit: std_logic_vector(3 downto 0); - signal selector: integer range 0 to 3 := 0; - signal counter : integer range 0 to 199999 := 0; + signal selector: integer := 0; + signal counter : integer := 0; begin with selector select @@ -56,10 +56,14 @@ begin alternateur : process(clock) begin if clock'event and clock = '1' then - if counter = 0 then - selector <= selector + 1; - end if; counter <= counter + 1; + if counter >= 199999 then + selector <= selector + 1; + if selector >= 3 then + selector <= 0; + end if; + counter <= 0; + end if; end if; end process; diff --git a/fpga/sevenseg_tb.gtkw b/fpga/sevenseg_tb.gtkw new file mode 100644 index 0000000..7211c6a --- /dev/null +++ b/fpga/sevenseg_tb.gtkw @@ -0,0 +1,38 @@ +[*] +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Sun Feb 25 12:47:52 2018 +[*] +[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/sevenseg_tb.vcd" +[dumpfile_mtime] "Sun Feb 25 12:44:56 2018" +[dumpfile_size] 111992791 +[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/sevenseg_tb.gtkw" +[timestart] 0 +[size] 1680 1012 +[pos] -1 -1 +*-42.000000 2550000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 213 +[signals_width] 126 +[sst_expanded] 1 +[sst_vpaned_height] 296 +@23 +dut.data[15:0] +@28 +dut.clock +@8420 +[color] 2 +dut.counter +@420 +[color] 2 +dut.selector +@22 +[color] 2 +dut.digit[3:0] +[color] 1 +dut.anode[3:0] +@28 +[color] 1 +dut.segment[6:0] +[color] 1 +dut.dot +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/fpga/sevenseg_tb.vhd b/fpga/sevenseg_tb.vhd new file mode 100644 index 0000000..110794d --- /dev/null +++ b/fpga/sevenseg_tb.vhd @@ -0,0 +1,59 @@ +-- Testbench automatically generated online +-- at http://vhdl.lapinoo.net +-- Generation date : 25.2.2018 12:42:48 GMT + +library ieee; +use ieee.std_logic_1164.all; + +entity sevenseg_tb is +end sevenseg_tb; + +architecture tb of sevenseg_tb is + + component sevenseg + port (data : in std_logic_vector (15 downto 0); + clock : in std_logic; + anode : out std_logic_vector (3 downto 0); + segment : out std_logic_vector (6 downto 0); + dot : out std_logic); + end component; + + signal data : std_logic_vector (15 downto 0); + signal clock : std_logic; + signal anode : std_logic_vector (3 downto 0); + signal segment : std_logic_vector (6 downto 0); + signal dot : std_logic; + + constant TbPeriod : time := 20 ns; + signal TbClock : std_logic := '0'; + signal TbSimEnded : std_logic := '0'; + + constant SegPeriod : time := 4 ms; + constant FourSegPeriod : time := 4 * SegPeriod; + +begin + + dut : sevenseg + port map (data => data, + clock => clock, + anode => anode, + segment => segment, + dot => dot); + + -- Clock generation + TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; + + clock <= TbClock; + + stimuli : process + begin + data <= x"0123"; + + wait for 2 * FourSegPeriod; + + -- Stop the clock and hence terminate the simulation + TbSimEnded <= '1'; + wait; + end process; + +end tb;