mirror of
https://github.com/RobotechLille/cdf2018-principal
synced 2025-09-05 09:35:56 +02:00
Gestion correcte de l'asservissement
This commit is contained in:
parent
fe3ae8efe9
commit
aa519e33bf
27 changed files with 972 additions and 449 deletions
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@ -5,14 +5,13 @@ use IEEE.NUMERIC_STD.ALL;
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entity Principal is
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Generic(
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fFpga : INTEGER := 50_000_000;
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fBaud : INTEGER := 115200
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fFpga : INTEGER := 50_000_000
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);
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Port (
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CLK : in std_logic;
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BTN: in std_logic;
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RX: in std_logic;
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TX: out std_logic;
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SDA: inout std_logic;
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SCL: inout std_logic;
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LEFTCHA: in std_logic;
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LEFTCHB: in std_logic;
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RIGHTCHA: in std_logic;
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@ -25,11 +24,11 @@ entity Principal is
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BACKRECHO: in std_logic;
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ENAREF: out std_logic;
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ENA: out std_logic;
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IN1ENC: out std_logic;
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IN1: out std_logic;
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IN2: out std_logic;
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ENBREF: out std_logic;
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ENB: out std_logic;
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IN3END: out std_logic;
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IN3: out std_logic;
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IN4: out std_logic
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);
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end Principal;
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@ -41,7 +40,6 @@ architecture Behavioral of Principal is
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-- Encoder
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signal left : integer;
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signal right : integer;
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signal zerocoder : std_logic;
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component hedm is
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Port (
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@ -101,11 +99,9 @@ architecture Behavioral of Principal is
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-- Motor controller
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signal enAd : std_logic_vector(7 downto 0);
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signal in1enCd : std_logic_vector(7 downto 0);
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signal in2d : std_logic;
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signal enBd : std_logic_vector(7 downto 0);
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signal in3enDd : std_logic_vector(7 downto 0);
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signal in4d : std_logic;
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signal ind : std_logic_vector(7 downto 0);
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component PWM is
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port (
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clk : in std_logic;
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@ -115,54 +111,46 @@ architecture Behavioral of Principal is
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end component;
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-- CF
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component uart is
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generic (
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baud : positive := fBaud;
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clock_frequency : positive := fFpga
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);
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port (
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clock : in std_logic;
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reset : in std_logic;
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data_stream_in : in std_logic_vector(7 downto 0);
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data_stream_in_stb : in std_logic;
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data_stream_in_ack : out std_logic;
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data_stream_out : out std_logic_vector(7 downto 0);
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data_stream_out_stb : out std_logic;
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tx : out std_logic;
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rx : in std_logic
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);
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component I2CSLAVE
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generic(
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DEVICE: std_logic_vector(7 downto 0) := x"42"
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);
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port(
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MCLK : in std_logic;
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nRST : in std_logic;
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SDA_IN : in std_logic;
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SCL_IN : in std_logic;
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SDA_OUT : out std_logic;
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SCL_OUT : out std_logic;
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ADDRESS : out std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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DATA_IN : in std_logic_vector(7 downto 0);
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WR : out std_logic;
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RD : out std_logic
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);
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end component;
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signal sdaIn : std_logic;
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signal sclIn : std_logic;
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signal sdaOut : std_logic;
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signal sclOut : std_logic;
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signal address : std_logic_vector(7 downto 0);
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signal dataOut : std_logic_vector(7 downto 0);
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signal dataIn : std_logic_vector(7 downto 0);
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signal wr : std_logic;
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signal rd : std_logic;
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signal rdP : std_logic;
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signal txData : std_logic_vector(7 downto 0);
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signal txStb : std_logic := '0';
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signal txAck : std_logic := '0';
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signal rxData : std_logic_vector(7 downto 0);
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signal rxStb : std_logic := '0';
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-- Handling
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component communication is
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Port (
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clock : in std_logic;
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reset : in std_logic;
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left : in integer;
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right : in integer;
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zerocoder : out std_logic;
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front : in integer;
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back : in integer;
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txData : out std_logic_vector(7 downto 0);
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txStb : out std_logic;
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txAck : in std_logic;
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rxData : in std_logic_vector(7 downto 0);
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rxStb : in std_logic;
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enA : out std_logic_vector(7 downto 0);
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in1enC : out std_logic_vector(7 downto 0);
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in2 : out std_logic;
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enB : out std_logic_vector(7 downto 0);
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in3enD : out std_logic_vector(7 downto 0);
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in4 : out std_logic
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);
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end component;
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signal leftB : std_logic_vector(15 downto 0);
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signal rightB : std_logic_vector(15 downto 0);
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signal frontLRawB : std_logic_vector(15 downto 0);
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signal frontRRawB : std_logic_vector(15 downto 0);
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signal backLRawB : std_logic_vector(15 downto 0);
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signal backRRawB : std_logic_vector(15 downto 0);
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signal frontLB : std_logic_vector(15 downto 0);
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signal frontRB : std_logic_vector(15 downto 0);
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signal backLB : std_logic_vector(15 downto 0);
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signal backRB : std_logic_vector(15 downto 0);
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begin
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@ -184,7 +172,7 @@ begin
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chA => LEFTCHA,
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chB => LEFTCHB,
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reset => reset,
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zero => zerocoder,
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zero => '0',
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counts => left
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);
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@ -193,80 +181,80 @@ begin
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chA => RIGHTCHA,
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chB => RIGHTCHB,
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reset => reset,
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zero => zerocoder,
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zero => '0',
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counts => right
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);
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frontLCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => FRONTLECHO,
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distance => frontLRaw,
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trigger => FRONTTRIGGER,
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start => '1',
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finished => frontLFinished
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);
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clk => CLK,
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reset => reset,
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echo => FRONTLECHO,
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distance => frontLRaw,
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trigger => FRONTTRIGGER,
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start => '1',
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finished => frontLFinished
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);
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frontLFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => frontLRaw,
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signalOut => frontL,
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start => frontLFinished
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-- done => done
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);
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clock => CLK,
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reset => reset,
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signalIn => frontLRaw,
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signalOut => frontL,
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start => frontLFinished
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-- done => done
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);
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frontRCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => FRONTRECHO,
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distance => frontRRaw,
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-- trigger => FRONTTRIGGER,
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start => '1',
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finished => frontRFinished
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);
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clk => CLK,
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reset => reset,
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echo => FRONTRECHO,
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distance => frontRRaw,
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-- trigger => FRONTTRIGGER,
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start => '1',
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finished => frontRFinished
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);
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frontRFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => frontRRaw,
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signalOut => frontR,
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start => frontRFinished
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-- done => done
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);
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clock => CLK,
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reset => reset,
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signalIn => frontRRaw,
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signalOut => frontR,
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start => frontRFinished
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-- done => done
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);
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backLCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => BACKLECHO,
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distance => backLRaw,
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trigger => BACKTRIGGER,
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start => '1',
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finished => backLFinished
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);
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clk => CLK,
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reset => reset,
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echo => BACKLECHO,
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distance => backLRaw,
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trigger => BACKTRIGGER,
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start => '1',
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finished => backLFinished
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);
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backLFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => backLRaw,
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signalOut => backL,
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start => backLFinished
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-- done => done
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);
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clock => CLK,
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reset => reset,
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signalIn => backLRaw,
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signalOut => backL,
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start => backLFinished
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-- done => done
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);
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backRCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => BACKRECHO,
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distance => backRRaw,
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-- trigger => BACKTRIGGER,
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start => '1',
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finished => backRFinished
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);
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clk => CLK,
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reset => reset,
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echo => BACKRECHO,
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distance => backRRaw,
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-- trigger => BACKTRIGGER,
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start => '1',
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finished => backRFinished
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);
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backRFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => backRRaw,
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signalOut => backR,
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start => backRFinished
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-- done => done
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);
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clock => CLK,
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reset => reset,
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signalIn => backRRaw,
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signalOut => backR,
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start => backRFinished
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-- done => done
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);
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enAp : PWM port map (
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clk => pwmClk,
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data => enAd,
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@ -274,12 +262,8 @@ begin
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);
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ENAREF <= '1';
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in1enCp : PWM port map (
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clk => pwmClk,
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data => in1enCd,
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pulse => IN1ENC
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);
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IN2 <= in2d;
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IN1 <= ind(0);
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IN2 <= ind(1);
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enBp : PWM port map (
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clk => pwmClk,
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@ -288,48 +272,69 @@ begin
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);
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ENBREF <= '1';
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in3enDp : PWM port map (
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clk => pwmClk,
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data => in3enDd,
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pulse => IN3END
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IN3 <= ind(2);
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IN4 <= ind(3);
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FA : i2cslave port map (
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MCLK => clk,
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nRST => not reset,
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SDA_IN => sdaIn,
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SCL_IN => sclIn,
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SDA_OUT => sdaOut,
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SCL_OUT => sclOut,
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ADDRESS => address,
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DATA_OUT => dataOut,
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DATA_IN => dataIn,
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WR => wr,
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RD => rd
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);
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IN4 <= in4d;
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SCL <= 'Z' when sclOut = '1' else '0';
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sclIn <= to_UX01(SCL);
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SDA <= 'Z' when sdaOut = '1' else '0';
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sdaIn <= to_UX01(SDA);
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leftB <= std_logic_vector(to_signed(left, 16));
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rightB <= std_logic_vector(to_signed(right, 16));
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frontLRawB <= std_logic_vector(to_unsigned(frontLRaw, 16));
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frontRRawB <= std_logic_vector(to_unsigned(frontRRaw, 16));
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backLRawB <= std_logic_vector(to_unsigned(backLRaw, 16));
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backRRawB <= std_logic_vector(to_unsigned(backRRaw, 16));
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frontLB <= std_logic_vector(to_unsigned(frontL, 16));
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frontRB <= std_logic_vector(to_unsigned(frontR, 16));
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backLB <= std_logic_vector(to_unsigned(backL, 16));
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backRB <= std_logic_vector(to_unsigned(backR, 16));
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dataIn <= x"50" when address = x"00" else
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leftB(15 downto 8) when address = x"10" else
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leftB(7 downto 0) when address = x"11" else
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rightB(15 downto 8) when address = x"12" else
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rightB(7 downto 0) when address = x"13" else
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frontLRawB(15 downto 8) when address = x"20" else
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frontLRawB(7 downto 0) when address = x"21" else
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frontRRawB(15 downto 8) when address = x"22" else
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frontRRawB(7 downto 0) when address = x"23" else
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backLRawB(15 downto 8) when address = x"24" else
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backLRawB(7 downto 0) when address = x"25" else
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backRRawB(15 downto 8) when address = x"26" else
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backRRawB(7 downto 0) when address = x"27" else
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frontLB(15 downto 8) when address = x"30" else
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frontLB(7 downto 0) when address = x"31" else
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frontRB(15 downto 8) when address = x"32" else
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frontRB(7 downto 0) when address = x"33" else
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backLB(15 downto 8) when address = x"34" else
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backLB(7 downto 0) when address = x"35" else
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backRB(15 downto 8) when address = x"36" else
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backRB(7 downto 0) when address = x"37" else
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ind when address = x"60" else
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enAd when address = x"61" else
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enBd when address = x"62" else
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(others => '0');
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ind <= dataOut when (address = x"60" and wr = '1') else ind;
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enAd <= dataOut when (address = x"61" and wr = '1') else enAd;
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enBd <= dataOut when (address = x"62" and wr = '1') else enBd;
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FA: uart port map(
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clock => CLK,
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reset => reset,
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data_stream_in => txData,
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data_stream_in_stb => txStb,
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data_stream_in_ack => txAck,
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data_stream_out => rxData,
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data_stream_out_stb => rxStb,
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tx => TX,
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rx => RX
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);
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frontMin <= frontLRaw when frontLRaw < frontRRaw else frontRRaw;
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backMin <= backLRaw when backLRaw < backRRaw else backRRaw;
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com: communication port map(
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clock => CLK,
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reset => reset,
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left => left,
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right => right,
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zerocoder => zerocoder,
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front => frontMin,
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back => backMin,
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txData => txData,
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txStb => txStb,
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txAck => txAck,
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rxData => rxData,
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rxStb => rxStb,
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enA => enAd,
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in1enC => in1enCd,
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in2 => in2d,
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enB => enBd,
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in3enD => in3enDd,
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in4 => in4d
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);
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end Behavioral;
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|
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@ -97,6 +97,12 @@ begin
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txStb <= '0';
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zerocoder <= '0';
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txData <= x"00";
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enA <= (others => '0');
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in1enC <= (others => '0');
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enB <= (others => '0');
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in3enD <= (others => '0');
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in2 <= '0';
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in4 <= '0';
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else
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if rising_edge(clock) then
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zerocoder <= '0';
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|
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@ -23,7 +23,7 @@ architecture Behavioral of fir is
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constant N : INTEGER := 4; -- Nombre de coefficients
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constant M : INTEGER := 2**6; -- Facteur multiplicatif
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type INT_ARRAY is array (N-1 downto 0) of integer;
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constant coefficients : INT_ARRAY := (16,16,16,16);
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constant coefficients : INT_ARRAY := (32,16,8,8);
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-- ↑ Coefficients du fir multipliés par M
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signal echantillons : INT_ARRAY := (others => 0); -- stockage des entrées retardées
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|
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283
fpga/i2c.vhd
Normal file
283
fpga/i2c.vhd
Normal file
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@ -0,0 +1,283 @@
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--###############################
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--# Project Name : I2C slave
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--# File : i2cslave.vhd
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--# Project : i2c slave for FPGA
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--# Engineer : Philippe THIRION
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--# Modification History
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--###############################
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-- copyright Philippe Thirion
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-- github.com/tirfil
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--
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-- Copyright 2016 Philippe THIRION
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--
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-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
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-- (at your option) any later version.
|
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-- This program is distributed in the hope that it will be useful,
|
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
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|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity I2CSLAVE is
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generic(
|
||||
DEVICE : std_logic_vector(7 downto 0) := x"38"
|
||||
);
|
||||
port(
|
||||
MCLK : in std_logic;
|
||||
nRST : in std_logic;
|
||||
SDA_IN : in std_logic;
|
||||
SCL_IN : in std_logic;
|
||||
SDA_OUT : out std_logic;
|
||||
SCL_OUT : out std_logic;
|
||||
ADDRESS : out std_logic_vector(7 downto 0);
|
||||
DATA_OUT : out std_logic_vector(7 downto 0);
|
||||
DATA_IN : in std_logic_vector(7 downto 0);
|
||||
WR : out std_logic;
|
||||
RD : out std_logic
|
||||
);
|
||||
end I2CSLAVE;
|
||||
|
||||
architecture rtl of I2CSLAVE is
|
||||
|
||||
type tstate is ( S_IDLE, S_START, S_SHIFTIN, S_RW, S_SENDACK, S_SENDACK2, S_SENDNACK,
|
||||
S_ADDRESS, S_WRITE, S_SHIFTOUT, S_READ, S_WAITACK
|
||||
);
|
||||
|
||||
type toperation is (OP_READ, OP_WRITE);
|
||||
|
||||
signal state : tstate;
|
||||
signal next_state : tstate;
|
||||
signal operation : toperation;
|
||||
|
||||
signal rising_scl, falling_scl : std_logic;
|
||||
signal address_i : std_logic_vector(7 downto 0);
|
||||
signal next_address : std_logic_vector(7 downto 0);
|
||||
signal counter : integer range 0 to 7;
|
||||
signal start_cond : std_logic;
|
||||
signal stop_cond : std_logic;
|
||||
signal sda_q, sda_qq, sda_qqq : std_logic;
|
||||
signal scl_q, scl_qq, scl_qqq : std_logic;
|
||||
signal shiftreg : std_logic_vector(7 downto 0);
|
||||
signal sda: std_logic;
|
||||
signal address_incr : std_logic;
|
||||
signal rd_d : std_logic;
|
||||
begin
|
||||
|
||||
ADDRESS <= address_i;
|
||||
|
||||
next_address <= (others=>'0') when (address_i = x"FF") else
|
||||
std_logic_vector(to_unsigned(to_integer(unsigned( address_i )) + 1, 8));
|
||||
|
||||
S_RSY: process(MCLK,nRST)
|
||||
begin
|
||||
if (nRST = '0') then
|
||||
sda_q <= '1';
|
||||
sda_qq <= '1';
|
||||
sda_qqq <= '1';
|
||||
scl_q <= '1';
|
||||
scl_qq <= '1';
|
||||
scl_qqq <= '1';
|
||||
elsif (MCLK'event and MCLK='1') then
|
||||
sda_q <= SDA_IN;
|
||||
sda_qq <= sda_q;
|
||||
sda_qqq <= sda_qq;
|
||||
scl_q <= SCL_IN;
|
||||
scl_qq <= scl_q;
|
||||
scl_qqq <= scl_qq;
|
||||
end if;
|
||||
end process S_RSY;
|
||||
|
||||
rising_scl <= scl_qq and not scl_qqq;
|
||||
falling_scl <= not scl_qq and scl_qqq;
|
||||
|
||||
START_BIT: process(MCLK,nRST)
|
||||
begin
|
||||
if (nRST = '0') then
|
||||
start_cond <= '0';
|
||||
elsif (MCLK'event and MCLK='1') then
|
||||
if (sda_qqq = '1' and sda_qq = '0' and scl_qq = '1') then
|
||||
start_cond <= '1';
|
||||
else
|
||||
start_cond <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process START_BIT;
|
||||
|
||||
STOP_BIT: process(MCLK,nRST)
|
||||
begin
|
||||
if (nRST = '0') then
|
||||
stop_cond <= '0';
|
||||
elsif (MCLK'event and MCLK='1') then
|
||||
if (sda_qqq = '0' and sda_qq = '1' and scl_qq = '1') then
|
||||
stop_cond <= '1';
|
||||
else
|
||||
stop_cond <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process STOP_BIT;
|
||||
|
||||
sda <= sda_qq;
|
||||
|
||||
RD_DELAY: process(MCLK, nRST)
|
||||
begin
|
||||
if (nRST = '0') then
|
||||
RD <= '0';
|
||||
elsif (MCLK'event and MCLK='1') then
|
||||
RD <= rd_d;
|
||||
end if;
|
||||
end process RD_DELAY;
|
||||
|
||||
OTO: process(MCLK, nRST)
|
||||
begin
|
||||
if (nRST = '0') then
|
||||
state <= S_IDLE;
|
||||
SDA_OUT <= '1';
|
||||
SCL_OUT <= '1';
|
||||
WR <= '0';
|
||||
rd_d <= '0';
|
||||
address_i <= (others=>'0');
|
||||
DATA_OUT <= (others=>'0');
|
||||
shiftreg <= (others=>'0');
|
||||
elsif (MCLK'event and MCLK='1') then
|
||||
if (stop_cond = '1') then
|
||||
state <= S_IDLE;
|
||||
SDA_OUT <= '1';
|
||||
SCL_OUT <= '1';
|
||||
operation <= OP_READ;
|
||||
WR <= '0';
|
||||
rd_d <= '0';
|
||||
address_incr <= '0';
|
||||
elsif(start_cond = '1') then
|
||||
state <= S_START;
|
||||
SDA_OUT <= '1';
|
||||
SCL_OUT <= '1';
|
||||
operation <= OP_READ;
|
||||
WR <= '0';
|
||||
rd_d <= '0';
|
||||
address_incr <= '0';
|
||||
elsif(state = S_IDLE) then
|
||||
state <= S_IDLE;
|
||||
SDA_OUT <= '1';
|
||||
SCL_OUT <= '1';
|
||||
operation <= OP_READ;
|
||||
WR <= '0';
|
||||
rd_d <= '0';
|
||||
address_incr <= '0';
|
||||
elsif(state = S_START) then
|
||||
shiftreg <= (others=>'0');
|
||||
state <= S_SHIFTIN;
|
||||
next_state <= S_RW;
|
||||
counter <= 6;
|
||||
elsif(state = S_SHIFTIN) then
|
||||
if (rising_scl = '1') then
|
||||
shiftreg(7 downto 1) <= shiftreg(6 downto 0);
|
||||
shiftreg(0) <= sda;
|
||||
if (counter = 0) then
|
||||
state <= next_state;
|
||||
counter <= 7;
|
||||
else
|
||||
counter <= counter - 1;
|
||||
end if;
|
||||
end if;
|
||||
elsif(state = S_RW) then
|
||||
if (rising_scl = '1') then
|
||||
if (shiftreg = DEVICE) then
|
||||
state <= S_SENDACK;
|
||||
if (sda = '1') then
|
||||
operation <= OP_READ;
|
||||
-- next_state <= S_READ; -- no needed
|
||||
rd_d <= '1';
|
||||
else
|
||||
operation <= OP_WRITE;
|
||||
next_state <= S_ADDRESS;
|
||||
address_incr <= '0';
|
||||
end if;
|
||||
else
|
||||
state <= S_SENDNACK;
|
||||
end if;
|
||||
end if;
|
||||
elsif(state = S_SENDACK) then
|
||||
WR <= '0';
|
||||
rd_d <= '0';
|
||||
if (falling_scl = '1') then
|
||||
SDA_OUT <= '0';
|
||||
counter <= 7;
|
||||
if (operation= OP_WRITE) then
|
||||
state <= S_SENDACK2;
|
||||
else -- OP_READ
|
||||
state <= S_SHIFTOUT;
|
||||
shiftreg <= DATA_IN;
|
||||
end if;
|
||||
end if;
|
||||
elsif(state = S_SENDACK2) then
|
||||
if (falling_scl = '1') then
|
||||
SDA_OUT <= '1';
|
||||
state <= S_SHIFTIN;
|
||||
shiftreg <= (others=>'0');
|
||||
if (address_incr = '1') then
|
||||
address_i <= next_address;
|
||||
end if;
|
||||
end if;
|
||||
elsif(state = S_SENDNACK) then
|
||||
if (falling_scl = '1') then
|
||||
SDA_OUT <= '1';
|
||||
state <= S_IDLE;
|
||||
end if;
|
||||
elsif(state = S_ADDRESS) then
|
||||
address_i <= shiftreg;
|
||||
next_state <= S_WRITE;
|
||||
state <= S_SENDACK;
|
||||
address_incr <= '0';
|
||||
elsif(state = S_WRITE) then
|
||||
DATA_OUT <= shiftreg;
|
||||
next_state <= S_WRITE;
|
||||
state <= S_SENDACK;
|
||||
WR <= '1';
|
||||
address_incr <= '1';
|
||||
elsif(state = S_SHIFTOUT) then
|
||||
if (falling_scl = '1') then
|
||||
SDA_OUT <= shiftreg(7);
|
||||
shiftreg(7 downto 1) <= shiftreg(6 downto 0);
|
||||
shiftreg(0) <= '1';
|
||||
if (counter = 0) then
|
||||
state <= S_READ;
|
||||
address_i <= next_address;
|
||||
rd_d <= '1';
|
||||
else
|
||||
counter <= counter - 1;
|
||||
end if;
|
||||
end if;
|
||||
elsif(state = S_READ) then
|
||||
rd_d <= '0';
|
||||
if (falling_scl = '1') then
|
||||
SDA_OUT <= '1';
|
||||
state <= S_WAITACK;
|
||||
end if;
|
||||
elsif(state = S_WAITACK) then
|
||||
if (rising_scl = '1') then
|
||||
if (sda = '0') then
|
||||
state <= S_SHIFTOUT;
|
||||
counter <= 7;
|
||||
shiftreg <= DATA_IN;
|
||||
else
|
||||
state <= S_IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process OTO;
|
||||
|
||||
|
||||
end rtl;
|
||||
|
|
@ -8,10 +8,10 @@ TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
|
|||
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<10>
|
||||
NET "RX" LOC = "P85" | IOSTANDARD = LVTTL ;
|
||||
NET "SCL" LOC = "P85" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<11>
|
||||
NET "TX" LOC = "P84" | IOSTANDARD = LVTTL ;
|
||||
NET "SDA" LOC = "P84" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<12>
|
||||
NET "LEFTCHA" LOC = "P83" | IOSTANDARD = LVTTL ;
|
||||
|
|
@ -44,7 +44,7 @@ NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ;
|
|||
NET "ENA" LOC = "P4" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<22>
|
||||
NET "IN1ENC" LOC = "P6" | IOSTANDARD = LVTTL ;
|
||||
NET "IN1" LOC = "P6" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<23>
|
||||
NET "IN2" LOC = "P98" | IOSTANDARD = LVTTL ;
|
||||
|
|
@ -56,7 +56,7 @@ NET "ENBREF" LOC = "P94" | IOSTANDARD = LVTTL ;
|
|||
NET "ENB" LOC = "P93" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<26>
|
||||
NET "IN3END" LOC = "P90" | IOSTANDARD = LVTTL ;
|
||||
NET "IN3" LOC = "P90" | IOSTANDARD = LVTTL ;
|
||||
|
||||
# IO<27>
|
||||
NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ;
|
||||
|
|
|
|||
|
|
@ -5,5 +5,5 @@ PROGRAMMER = mercpcl
|
|||
|
||||
TOPLEVEL = Principal
|
||||
# Prod
|
||||
VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd fir.vhd pwm.vhd
|
||||
VHDSOURCE = $(TOPLEVEL).vhd i2c.vhd hedm.vhd hcsr04.vhd fir.vhd pwm.vhd
|
||||
CONSTRAINTS = principal.ucf
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue