diff --git a/arduino/AFsignals.h b/arduino/AFsignals.h index a808fc8..0c7798d 100644 --- a/arduino/AFsignals.h +++ b/arduino/AFsignals.h @@ -28,9 +28,6 @@ // Pour le debug #define A2FD_PING 'P' -// Réinitialise la valeur des codeuses -#define A2FD_RESETCODER 'R' - // FPGA → Arduino // Erreur quelconque diff --git a/fpga/Makefile b/fpga/Makefile index 27af91a..c4b9f88 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -175,10 +175,10 @@ build/%_tb: build/%_tb.o $(addprefix build/,$(subst .vhd,.o,$(VHDSOURCE))) ghdl -e --workdir="$(shell dirname "$@")" -o "$(shell echo "$@" | tr A-Z a-z)" "$(basename $(notdir $<))" build/%_tb.vcd: build/%_tb - (cd "$(shell dirname "$<")"; ghdl -r "$(basename $(notdir $<))" --vcd="../$@" ) + (cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --vcd="../$@" ) build/%_tb.ghw: build/%_tb - (cd "$(shell dirname "$<")"; ghdl -r "$(basename $(notdir $<))" --wave="../$@" ) + (cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --wave="../$@" ) %_wave: build/%_tb.ghw gtkwave --save "$(notdir $(basename $<)).gtkw" "$<" diff --git a/fpga/Principal.vhd b/fpga/Principal.vhd index c10d9d2..59f7fd8 100644 --- a/fpga/Principal.vhd +++ b/fpga/Principal.vhd @@ -6,8 +6,9 @@ use IEEE.NUMERIC_STD.ALL; entity Principal is Port ( CLK : in STD_LOGIC; -- Clock BTN : in STD_LOGIC; -- Reset - -- FA - IO : inout STD_LOGIC_VECTOR (21 downto 20); + + -- FA & Encoder + IO : inout STD_LOGIC_VECTOR (21 downto 16); -- Debug LED : out STD_LOGIC_VECTOR (3 downto 0); AN : out STD_LOGIC_VECTOR (3 downto 0); @@ -27,10 +28,22 @@ architecture Behavioral of Principal is -- Encoder signal left : integer; signal right : integer; + signal zerocoder : std_logic; + + component hedm is + Port ( + clk : in STD_LOGIC; + chA : in STD_LOGIC; + chB : in STD_LOGIC; + reset : in STD_LOGIC; + zero : in STD_LOGIC; + counts : out integer + ); + end component; -- Sensors - signal front : integer; - signal back : integer; + signal front : integer := 0; + signal back : integer := 0; -- AF component uart is @@ -67,6 +80,7 @@ architecture Behavioral of Principal is reset : in std_logic; left : in integer; right : in integer; + zerocoder : out std_logic; front : in integer; back : in integer; txData : out std_logic_vector(7 downto 0); @@ -93,6 +107,24 @@ begin reset <= BTN; + leftCoder: hedm port map ( + clk => CLK, + chA => IO(19), + chB => IO(18), + reset => reset, + zero => zerocoder, + counts => left + ); + + rightCoder: hedm port map ( + clk => CLK, + chA => IO(17), + chB => IO(16), + reset => reset, + zero => zerocoder, + counts => right + ); + FA: uart port map( clock => CLK, reset => reset, @@ -110,6 +142,7 @@ begin reset => reset, left => left, right => right, + zerocoder => zerocoder, front => front, back => back, txData => txData, @@ -126,6 +159,8 @@ begin if reset = '1' then count <= 0; theled <= "0000"; + front <= 0; + back <= 0; elsif CLK'event and CLK = '1' then if count = 9999999 then count <= 0; diff --git a/fpga/Principal_tb.gtkw b/fpga/Principal_tb.gtkw index 1e27c3d..68fc097 100644 --- a/fpga/Principal_tb.gtkw +++ b/fpga/Principal_tb.gtkw @@ -1,62 +1,80 @@ [*] [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Sun Feb 25 14:12:54 2018 +[*] Tue Feb 27 09:39:06 2018 [*] -[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.vcd" -[dumpfile_mtime] "Sun Feb 25 14:10:51 2018" -[dumpfile_size] 38271255 +[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.ghw" +[dumpfile_mtime] "Tue Feb 27 09:38:56 2018" +[dumpfile_size] 32911228 [savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/Principal_tb.gtkw" [timestart] 0 -[size] 1680 1012 +[size] 1600 862 [pos] -1 -1 -*-40.000000 3481820000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dut. +*-41.636795 7980000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.principal_tb. +[treeopen] top.principal_tb.dut. +[treeopen] top.principal_tb.dut.fa. [sst_width] 213 [signals_width] 198 [sst_expanded] 1 [sst_vpaned_height] 296 @28 -[color] 4 -clk -dut.reset +top.principal_tb.dut.clk +top.principal_tb.dut.reset [color] 2 -dut.fa.rx_baud_tick +top.principal_tb.dut.fa.rx_baud_tick [color] 2 -dut.fa.rx +top.principal_tb.dut.fa.rx @8028 [color] 2 -dut.fa.uart_rx_count[2:0] +#{top.principal_tb.dut.fa.uart_rx_count[2:0]} top.principal_tb.dut.fa.uart_rx_count[2] top.principal_tb.dut.fa.uart_rx_count[1] top.principal_tb.dut.fa.uart_rx_count[0] @22 -[color] 2 -dut.fa.uart_rx_data_vec[7:0] -dut.rxdata[7:0] +[color] 1 +#{top.principal_tb.dut.rxdata[7:0]} top.principal_tb.dut.rxdata[7] top.principal_tb.dut.rxdata[6] top.principal_tb.dut.rxdata[5] top.principal_tb.dut.rxdata[4] top.principal_tb.dut.rxdata[3] top.principal_tb.dut.rxdata[2] top.principal_tb.dut.rxdata[1] top.principal_tb.dut.rxdata[0] @820 -dut.rxdata[7:0] +[color] 1 +#{top.principal_tb.dut.rxdata[7:0]} top.principal_tb.dut.rxdata[7] top.principal_tb.dut.rxdata[6] top.principal_tb.dut.rxdata[5] top.principal_tb.dut.rxdata[4] top.principal_tb.dut.rxdata[3] top.principal_tb.dut.rxdata[2] top.principal_tb.dut.rxdata[1] top.principal_tb.dut.rxdata[0] @28 -dut.rxstb -@420 -[color] 5 -dut.com.readoffset -[color] 5 -dut.com.sendoffset +[color] 1 +top.principal_tb.dut.com.rxstb @22 -[color] 4 -dut.txdata[7:0] +[color] 1 +#{top.principal_tb.dut.txdata[7:0]} top.principal_tb.dut.txdata[7] top.principal_tb.dut.txdata[6] top.principal_tb.dut.txdata[5] top.principal_tb.dut.txdata[4] top.principal_tb.dut.txdata[3] top.principal_tb.dut.txdata[2] top.principal_tb.dut.txdata[1] top.principal_tb.dut.txdata[0] @820 -[color] 4 -dut.txdata[7:0] +[color] 1 +#{top.principal_tb.dut.txdata[7:0]} top.principal_tb.dut.txdata[7] top.principal_tb.dut.txdata[6] top.principal_tb.dut.txdata[5] top.principal_tb.dut.txdata[4] top.principal_tb.dut.txdata[3] top.principal_tb.dut.txdata[2] top.principal_tb.dut.txdata[1] top.principal_tb.dut.txdata[0] @28 -dut.txstb -dut.txack +[color] 1 +top.principal_tb.dut.txstb +[color] 1 +top.principal_tb.dut.txack [color] 2 -dut.fa.tx -[color] 2 -dut.fa.tx_baud_tick +top.principal_tb.dut.fa.tx_baud_tick @8028 [color] 2 -dut.fa.uart_tx_count[2:0] +#{top.principal_tb.dut.fa.uart_tx_count[2:0]} top.principal_tb.dut.fa.uart_tx_count[2] top.principal_tb.dut.fa.uart_tx_count[1] top.principal_tb.dut.fa.uart_tx_count[0] @22 [color] 2 -dut.fa.uart_tx_data_vec[7:0] +#{top.principal_tb.dut.fa.uart_tx_data_vec[7:0]} top.principal_tb.dut.fa.uart_tx_data_vec[7] top.principal_tb.dut.fa.uart_tx_data_vec[6] top.principal_tb.dut.fa.uart_tx_data_vec[5] top.principal_tb.dut.fa.uart_tx_data_vec[4] top.principal_tb.dut.fa.uart_tx_data_vec[3] top.principal_tb.dut.fa.uart_tx_data_vec[2] top.principal_tb.dut.fa.uart_tx_data_vec[1] top.principal_tb.dut.fa.uart_tx_data_vec[0] +@28 +[color] 2 +top.principal_tb.dut.fa.tx +[color] 6 +top.principal_tb.dut.zerocoder +[color] 6 +top.principal_tb.dut.leftcoder.cha +[color] 6 +top.principal_tb.dut.leftcoder.chb +@8420 +[color] 6 +top.principal_tb.dut.left +@28 +[color] 6 +top.principal_tb.dut.rightcoder.cha +[color] 6 +top.principal_tb.dut.rightcoder.chb +@8421 +[color] 6 +top.principal_tb.dut.right [pattern_trace] 1 [pattern_trace] 0 diff --git a/fpga/Principal_tb.vhd b/fpga/Principal_tb.vhd index 6304b19..d35f18e 100644 --- a/fpga/Principal_tb.vhd +++ b/fpga/Principal_tb.vhd @@ -6,14 +6,14 @@ library ieee; use ieee.std_logic_1164.all; entity Principal_tb is -end Principal_tb; + end Principal_tb; architecture tb of Principal_tb is component Principal port (CLK : in std_logic; BTN : in std_logic; - IO : inout std_logic_vector (21 downto 20); + IO : inout std_logic_vector (21 downto 16); LED : out std_logic_vector (3 downto 0); AN : out std_logic_vector (3 downto 0); A_TO_G : out std_logic_vector (6 downto 0); @@ -22,7 +22,7 @@ architecture tb of Principal_tb is signal CLK : std_logic; signal BTN : std_logic; - signal IO : std_logic_vector (21 downto 20); + signal IO : std_logic_vector (21 downto 16); signal LED : std_logic_vector (3 downto 0); signal AN : std_logic_vector (3 downto 0); signal A_TO_G : std_logic_vector (6 downto 0); @@ -36,6 +36,8 @@ architecture tb of Principal_tb is constant CharacterPeriod : time := 10 * BaudPeriod; signal rx : std_logic; signal tx : std_logic; + + constant CoderPeriod : time := 27611 ns; begin dut : Principal @@ -55,9 +57,49 @@ begin IO(20) <= rx; tx <= IO(21); + leftCoder : process + begin + while TbSimEnded = '0' loop + IO(19) <= '1'; + wait for CoderPeriod; + IO(18) <= '1'; + wait for CoderPeriod; + IO(19) <= '0'; + wait for CoderPeriod; + IO(18) <= '0'; + wait for CoderPeriod; + end loop; + wait; + end process; + + rightCoder : process + begin + while TbSimEnded = '0' loop + IO(16) <= '0'; + wait for CoderPeriod; + IO(17) <= '0'; + wait for CoderPeriod; + IO(16) <= '1'; + wait for CoderPeriod; + IO(17) <= '1'; + wait for CoderPeriod; + end loop; + wait; + end process; stimuli : process - variable sending : std_logic_vector(7 downto 0); + procedure send + (char : std_logic_vector(7 downto 0)) is + begin + rx <= '0'; -- Start bit + wait for BaudPeriod; + for I in 0 to 7 loop + rx <= char(I); + wait for BaudPeriod; + end loop; + rx <= '1'; -- Stop bit + wait for BaudPeriod; + end procedure; begin rx <= '1'; @@ -69,40 +111,39 @@ begin wait for 2 * BaudPeriod; - -- Send 'P' - rx <= '0'; -- Start bit - sending := x"50"; -- 'P' - wait for BaudPeriod; - for I in 0 to 7 loop - rx <= sending(I); - wait for BaudPeriod; - end loop; - rx <= '1'; -- Stop bit - wait for BaudPeriod; - -- Wait for 1 byte receive + -- Send 'P' + send(x"50"); -- 'P' wait for CharacterPeriod; -- Wait margin wait for 2 * BaudPeriod; - -- Send '?' - rx <= '0'; -- Start bit - sending := x"3F"; -- '?' - wait for BaudPeriod; - for I in 0 to 7 loop - rx <= sending(I); - wait for BaudPeriod; - end loop; - rx <= '1'; -- Stop bit - wait for BaudPeriod; - -- Wait for 2 bytes receive + -- Send '?' + send(x"3F"); -- '?' wait for 2 * CharacterPeriod; -- Wait margin wait for 2 * BaudPeriod; + + -- Send 'C' + send(x"43"); -- '?' + wait for 5 * CharacterPeriod; + + -- Wait margin + wait for 5 * BaudPeriod; + + + -- Send 'D' + send(x"44"); -- '?' + wait for 5 * CharacterPeriod; + + -- Wait margin + wait for 5 * BaudPeriod; + + -- Stop the clock and hence terminate the simulation TbSimEnded <= '1'; wait; diff --git a/fpga/communication.vhd b/fpga/communication.vhd index 53ba3ca..54d0a6d 100644 --- a/fpga/communication.vhd +++ b/fpga/communication.vhd @@ -9,6 +9,7 @@ entity communication is reset : in std_logic; left : in integer; right : in integer; + zerocoder : out std_logic; front : in integer; back : in integer; txData : out std_logic_vector(7 downto 0); @@ -30,7 +31,7 @@ architecture Behavioral of communication is constant F2AT_CAPT : std_logic_vector(7 downto 0) := x"63"; -- 'c' type readStates is (readIdle); - signal readState : readStates := readIdle; + signal readState : readStates := readIdle; -- TODO Make sure is correctly reset when reworking this signal readOffset : integer := 0; type sendMessages is (none, A2FD_PINGs, F2AI_CODERs, F2AI_CAPTs, F2AD_ERR_UNKNOWN_CODEs); @@ -91,8 +92,20 @@ begin begin if reset = '1' then readState <= readIdle; + sendMessage := none; + sendOffset := 0; + sendSize := 0; + sendTail := 0; + sendHead := 0; + sendLooped := false; + frontTrigger <= 0; + backTrigger <= 0; + zerocoder <= '0'; + txData <= x"00"; else if rising_edge(clock) then + zerocoder <= '0'; + -- If read something if rxStb = '1' then if readState = readIdle then @@ -120,9 +133,15 @@ begin sendSize := 1; when F2AI_CAPTs => sendData(7 downto 0) := F2AI_CAPT; - sendData(23 downto 8) := std_logic_vector(to_unsigned(front, 16)); + sendData(23 downto 8) := std_logic_vector(to_signed(front, 16)); sendData(39 downto 24) := std_logic_vector(to_unsigned(back, 16)); sendSize := 5; + when F2AI_CODERs => + zerocoder <= '1'; + sendData(7 downto 0) := F2AI_CODER; + sendData(23 downto 8) := std_logic_vector(to_signed(left, 16)); + sendData(39 downto 24) := std_logic_vector(to_signed(right, 16)); + sendSize := 5; when others => -- Including F2AD_ERR_UNKNOWN_CODEs sendData(7 downto 0) := F2AD_ERR; sendData(15 downto 8) := ERR_UNKNOWN_CODE; diff --git a/fpga/communication_tb.gtkw b/fpga/communication_tb.gtkw index c4a8ae6..c0cc5da 100644 --- a/fpga/communication_tb.gtkw +++ b/fpga/communication_tb.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Mon Feb 26 19:15:08 2018 +[*] Tue Feb 27 08:58:38 2018 [*] [dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/communication_tb.ghw" -[dumpfile_mtime] "Mon Feb 26 19:15:01 2018" -[dumpfile_size] 4519 +[dumpfile_mtime] "Tue Feb 27 08:58:14 2018" +[dumpfile_size] 5411 [savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/communication_tb.gtkw" [timestart] 0 [size] 1600 862 [pos] -1 -1 -*-29.277596 1395000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-29.549107 930000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] top. [treeopen] top.communication_tb. [treeopen] top.communication_tb.dut. @@ -45,5 +45,8 @@ top.communication_tb.dut.readoffset top.communication_tb.dut.txstb [color] 1 top.communication_tb.dut.txack +@29 +[color] 2 +top.communication_tb.dut.zerocoder [pattern_trace] 1 [pattern_trace] 0 diff --git a/fpga/communication_tb.vhd b/fpga/communication_tb.vhd index 1ffa495..adeb056 100644 --- a/fpga/communication_tb.vhd +++ b/fpga/communication_tb.vhd @@ -17,6 +17,7 @@ architecture tb of communication_tb is left : in integer; right : in integer; front : in integer; + zerocoder : out std_logic; back : in integer; txData : out std_logic_vector (7 downto 0); txStb : out std_logic; @@ -33,6 +34,7 @@ architecture tb of communication_tb is signal back : integer; signal txData : std_logic_vector (7 downto 0); signal txStb : std_logic; + signal zerocoder : std_logic; signal txAck : std_logic; signal rxData : std_logic_vector (7 downto 0); signal rxStb : std_logic; @@ -54,6 +56,7 @@ begin back => back, txData => txData, txStb => txStb, + zerocoder => zerocoder, txAck => txAck, rxData => rxData, rxStb => rxStb); @@ -92,7 +95,6 @@ begin assert txData = x"50" report "Not sent 'P'" severity error; assert txStb = '1' report "Not sending" severity error; - report "Acknowledging send" severity note; wait for 100 ns; txAck <= '1'; wait for TbPeriod; @@ -115,7 +117,6 @@ begin assert txData = x"45" report "Not sent 'E'" severity error; assert txStb = '1' report "Not sending" severity error; - report "Acknowledging send" severity note; wait for 100 ns; txAck <= '1'; wait for TbPeriod; @@ -125,7 +126,6 @@ begin assert txData = x"43" report "Not sent 'C'" severity error; assert txStb = '1' report "Not sending" severity error; - report "Acknowledging send" severity note; wait for 100 ns; txAck <= '1'; wait for TbPeriod; @@ -150,7 +150,6 @@ begin assert txData = x"50" report "Not sent 'P'" severity error; assert txStb = '1' report "Not sending" severity error; - report "Acknowledging send" severity note; wait for 100 ns; txAck <= '1'; wait for TbPeriod; @@ -176,7 +175,36 @@ begin assert txData = shouldReceive(I) report "Not sent correct data, got " & integer'image(to_integer(unsigned(txData))) & ", expected " & integer'image(to_integer(unsigned(shouldReceive(I))))severity error; assert txStb = '1' report "Not sending" severity error; - report "Acknowledging send" severity note; + wait for 100 ns; + txAck <= '1'; + wait for TbPeriod; + txAck <= '0'; + end loop; + + wait for 100 ns; + assert txStb = '0' report "Not stopping send" severity error; + + -- Test encoder + left <= 1152; + right <= 11614; + + report "TEST Receiving 'D'" severity note; + rxData <= x"44"; + rxStb <= '1'; + wait for TbPeriod; + assert zerocoder = '1' report "Not reseting coder values" severity error; + left <= 0; + right <= 0; + rxStb <= '0'; + wait for TbPeriod; + assert zerocoder = '0' report "Not stopping reseting coder values" severity error; + + shouldReceive(0 to 4) := (x"44", x"80", x"04", x"5E", x"2D"); + for I in 0 to 4 loop + wait for 100 ns; + assert txData = shouldReceive(I) report "Not sent correct data, got " & integer'image(to_integer(unsigned(txData))) & ", expected " & integer'image(to_integer(unsigned(shouldReceive(I))))severity error; + assert txStb = '1' report "Not sending" severity error; + wait for 100 ns; txAck <= '1'; wait for TbPeriod; diff --git a/fpga/hedm.vhd b/fpga/hedm.vhd index c2127ed..a54ecf5 100644 --- a/fpga/hedm.vhd +++ b/fpga/hedm.vhd @@ -13,20 +13,22 @@ entity hedm is clk : in STD_LOGIC; -- Horloge, la fréquence n'importe pas chA : in STD_LOGIC; -- Canal A chB : in STD_LOGIC; -- Canal B - reset : in STD_LOGIC; + reset : in STD_LOGIC; -- Hard reset + zero : in STD_LOGIC; -- Force la valeur à zéro sans réinitialiser le fonctionnement counts : out integer ); end hedm; architecture Behavioral of hedm is - signal counter : integer := 0; signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant begin processInput : process(clk, reset) + variable counter : integer := 0; begin if reset = '1' then - counter <= 0; + counter := 0; + counts <= 0; An <= '0'; Bn <= '0'; Ap <= '0'; @@ -39,39 +41,44 @@ begin An <= chA; Bn <= chB; + if zero = '1' then + counter := 0; + end if; + -- On pourrait optimiser la logique avec un tableau de Karnaugh ou autres méthodes -- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un -- tout aussi bon travail, on garde donc le code suivant pour la lisibilité if (Ap = '0' and An = '1') then -- Front montant A if (Bn = '0') then - counter <= counter + 1; + counter := counter + 1; else - counter <= counter - 1; + counter := counter - 1; end if; elsif (Ap = '1' and An = '0') then -- Front descendant A if (Bn = '1') then - counter <= counter + 1; + counter := counter + 1; else - counter <= counter - 1; + counter := counter - 1; end if; elsif (Bp = '0' and Bn = '1') then -- Front montant B if (An = '1') then - counter <= counter + 1; + counter := counter + 1; else - counter <= counter - 1; + counter := counter - 1; end if; elsif (Bp = '1' and Bn = '0') then -- Front descendant B if (An = '0') then - counter <= counter + 1; + counter := counter + 1; else - counter <= counter - 1; + counter := counter - 1; end if; end if; + + counts <= counter; + end if; end process; - counts <= counter; - end Behavioral; diff --git a/fpga/hedm_tb.gtkw b/fpga/hedm_tb.gtkw index 7e953ae..62f93c6 100644 --- a/fpga/hedm_tb.gtkw +++ b/fpga/hedm_tb.gtkw @@ -1,25 +1,43 @@ [*] [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Sat Feb 24 16:20:02 2018 +[*] Tue Feb 27 08:32:01 2018 [*] -[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.vcd" -[dumpfile_mtime] "Sat Feb 24 16:19:31 2018" -[dumpfile_size] 10717 -[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.gtkw" +[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.ghw" +[dumpfile_mtime] "Tue Feb 27 08:31:12 2018" +[dumpfile_size] 4287 +[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/hedm_tb.gtkw" [timestart] 0 [size] 1600 862 [pos] -1 -1 -*-28.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-28.781492 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.hedm_tb. [sst_width] 213 [signals_width] 78 [sst_expanded] 1 [sst_vpaned_height] 244 @28 -clk -reset -cha -chb -@421 -counts +top.hedm_tb.dut.clk +top.hedm_tb.dut.reset +[color] 4 +top.hedm_tb.dut.zero +[color] 5 +top.hedm_tb.dut.cha +[color] 5 +top.hedm_tb.dut.chb +[color] 2 +top.hedm_tb.dut.ap +[color] 2 +top.hedm_tb.dut.bp +[color] 2 +top.hedm_tb.dut.an +[color] 2 +top.hedm_tb.dut.bn +@420 +[color] 1 +top.hedm_tb.dut.counts +@8421 +[color] 1 +top.hedm_tb.dut.counts [pattern_trace] 1 [pattern_trace] 0 diff --git a/fpga/hedm_tb.vhd b/fpga/hedm_tb.vhd index e2f6b17..25714c7 100644 --- a/fpga/hedm_tb.vhd +++ b/fpga/hedm_tb.vhd @@ -15,6 +15,7 @@ architecture tb of hedm_tb is chA : in std_logic; chB : in std_logic; reset : in std_logic; + zero : in std_logic; counts : out integer); end component; @@ -22,6 +23,7 @@ architecture tb of hedm_tb is signal chA : std_logic; signal chB : std_logic; signal reset : std_logic; + signal zero : std_logic; signal counts : integer; constant TbPeriod : time := 20 ns; @@ -35,6 +37,7 @@ begin chA => chA, chB => chB, reset => reset, + zero => zero, counts => counts); -- Clock generation @@ -48,6 +51,7 @@ begin begin chA <= '0'; chB <= '0'; + zero <= '0'; -- Reset generation reset <= '1'; @@ -70,8 +74,17 @@ begin wait for 5 * TbPeriod; assert counts = nbTours * 4 report "Sens avant faux, reçu " & integer'image(counts) severity error; + -- Test zero + zero <= '1'; + wait for TbPeriod; + zero <= '0'; + wait for TbPeriod; - -- Test sens avant + wait for 5 * TbPeriod; + assert counts = 0 report "Zero faux, reçu " & integer'image(counts) severity error; + + + -- Test sens arrière for I in 0 to nbTours-1 loop chB <= '1'; wait for TbPeriod; @@ -84,7 +97,27 @@ begin end loop; wait for 5 * TbPeriod; - assert counts = 0 report "Sens arrière faux, reçu " & integer'image(counts) severity error; + assert counts = -40 report "Sens arrière faux, reçu " & integer'image(counts) severity error; + + -- Test zero en éxecution + chA <= '1'; + wait for TbPeriod; + chB <= '1'; + wait for TbPeriod; + chA <= '0'; + zero <= '1'; + wait for TbPeriod; + chB <= '0'; + zero <= '0'; + wait for TbPeriod; + + wait for 5 * TbPeriod; + assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error; + + zero <= '1'; + wait for TbPeriod; + zero <= '0'; + wait for TbPeriod; -- Test aller-retours for I in 0 to nbTours-1 loop @@ -102,6 +135,7 @@ begin assert counts = 0 report "Aller-retours faux, reçu " & integer'image(counts) severity error; + -- Stop the clock and hence terminate the simulation TbSimEnded <= '1'; wait;