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https://github.com/RobotechLille/cdf2018-principal
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FPGA : HCSR04 et améliorations
This commit is contained in:
parent
d111629b12
commit
d477c9ec58
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@ -4,24 +4,27 @@ use IEEE.NUMERIC_STD.ALL;
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entity Principal is
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entity Principal is
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Port ( CLK : in STD_LOGIC; -- Clock
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Generic(
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BTN : in STD_LOGIC; -- Reset
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fFpga : INTEGER := 50_000_000;
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fBaud : INTEGER := 9600
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-- FA & Encoder
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);
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IO : inout STD_LOGIC_VECTOR (21 downto 16);
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Port (
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-- Debug
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CLK : in std_logic;
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LED : out STD_LOGIC_VECTOR (3 downto 0);
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BTN: in std_logic;
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AN : out STD_LOGIC_VECTOR (3 downto 0);
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RX: in std_logic;
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A_TO_G : out STD_LOGIC_VECTOR (6 downto 0);
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TX: out std_logic;
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DOT : out STD_LOGIC
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LEFTCHA: in std_logic;
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LEFTCHB: in std_logic;
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RIGHTCHA: in std_logic;
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RIGHTCHB: in std_logic;
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FRONTTRIGGER: out std_logic;
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FRONTECHO: in std_logic;
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BACKTRIGGER: out std_logic;
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BACKECHO: in std_logic
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);
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);
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end Principal;
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end Principal;
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architecture Behavioral of Principal is
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architecture Behavioral of Principal is
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-- Blink led
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signal count : integer := 0;
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signal theled: std_logic_vector(3 downto 0) := "0000";
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-- General
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-- General
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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@ -44,12 +47,26 @@ architecture Behavioral of Principal is
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-- Sensors
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-- Sensors
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signal front : integer := 0;
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signal front : integer := 0;
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signal back : integer := 0;
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signal back : integer := 0;
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component hcsr04 IS
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generic(
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fFpga : INTEGER := fFpga
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);
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port(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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echo : IN STD_LOGIC;
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distance : OUT INTEGER;
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trigger : OUT STD_LOGIC;
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start : IN STD_LOGIC;
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finished : OUT STD_LOGIC
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);
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end component;
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-- AF
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-- AF
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component uart is
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component uart is
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generic (
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generic (
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baud : positive := 9600;
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baud : positive := fBaud;
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clock_frequency : positive := 50_000_000
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clock_frequency : positive := fFpga
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);
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);
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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@ -64,8 +81,6 @@ architecture Behavioral of Principal is
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);
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);
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end component;
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end component;
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constant BAUD_COUNT: std_logic_vector := x"1458"; -- 96000 Baud at 50 MHz
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signal txData : std_logic_vector(7 downto 0);
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signal txData : std_logic_vector(7 downto 0);
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signal txStb : std_logic := '0';
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signal txStb : std_logic := '0';
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signal txAck : std_logic := '0';
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signal txAck : std_logic := '0';
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@ -91,26 +106,14 @@ architecture Behavioral of Principal is
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);
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);
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end component;
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end component;
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-- Debug
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component sevenseg is
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Port (
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data : in STD_LOGIC_VECTOR (15 downto 0);
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clock : in STD_LOGIC;
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anode : out STD_LOGIC_VECTOR (3 downto 0);
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segment : out STD_LOGIC_VECTOR (6 downto 0);
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dot : out STD_LOGIC
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);
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end component;
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signal sevensegdata: std_logic_vector(15 downto 0);
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signal fullseg: std_logic_vector(7 downto 0);
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begin
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begin
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reset <= BTN;
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reset <= BTN;
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leftCoder: hedm port map (
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leftCoder: hedm port map (
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clk => CLK,
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clk => CLK,
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chA => IO(19),
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chA => LEFTCHA,
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chB => IO(18),
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chB => LEFTCHB,
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reset => reset,
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reset => reset,
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zero => zerocoder,
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zero => zerocoder,
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counts => left
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counts => left
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@ -118,12 +121,31 @@ begin
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rightCoder: hedm port map (
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rightCoder: hedm port map (
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clk => CLK,
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clk => CLK,
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chA => IO(17),
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chA => RIGHTCHA,
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chB => IO(16),
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chB => RIGHTCHB,
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reset => reset,
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reset => reset,
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zero => zerocoder,
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zero => zerocoder,
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counts => right
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counts => right
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);
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);
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frontCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => FRONTECHO,
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distance => front,
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trigger => FRONTTRIGGER,
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start => '1'
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-- finished =>
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);
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backCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => BACKECHO,
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distance => back,
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trigger => BACKTRIGGER,
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start => '1'
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-- finished =>
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);
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FA: uart port map(
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FA: uart port map(
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clock => CLK,
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clock => CLK,
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@ -133,8 +155,8 @@ begin
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data_stream_in_ack => txAck,
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data_stream_in_ack => txAck,
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data_stream_out => rxData,
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data_stream_out => rxData,
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data_stream_out_stb => rxStb,
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data_stream_out_stb => rxStb,
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tx => IO(21),
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tx => TX,
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rx => IO(20)
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rx => RX
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);
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);
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com: communication port map(
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com: communication port map(
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@ -151,40 +173,5 @@ begin
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rxData => rxData,
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rxData => rxData,
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rxStb => rxStb
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rxStb => rxStb
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);
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);
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-- Debug
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blinkled : process(CLK, reset)
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begin
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if reset = '1' then
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count <= 0;
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theled <= "0000";
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front <= 0;
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back <= 0;
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elsif CLK'event and CLK = '1' then
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if count = 9999999 then
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count <= 0;
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theled(3) <= not theled(3);
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theled(2 downto 0) <= "000";
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else
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count <= count + 1;
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theled(2 downto 0) <= theled(2 downto 0) or (txStb & rxStb & txAck);
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end if;
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end if;
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end process;
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LED <= theled;
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debugSeg: sevenseg port map(
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data => sevensegdata,
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clock => CLK,
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anode => AN,
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segment => A_TO_G,
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dot => DOT
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);
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sevensegdata(15 downto 8) <= rxData;
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sevensegdata(7 downto 0) <= txData;
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end Behavioral;
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end Behavioral;
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@ -1,19 +1,18 @@
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[*]
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Tue Feb 27 09:39:06 2018
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[*] Tue Feb 27 18:30:48 2018
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[*]
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[*]
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[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.ghw"
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[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.ghw"
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[dumpfile_mtime] "Tue Feb 27 09:38:56 2018"
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[dumpfile_mtime] "Tue Feb 27 18:29:45 2018"
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[dumpfile_size] 32911228
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[dumpfile_size] 4891772
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[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/Principal_tb.gtkw"
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[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/Principal_tb.gtkw"
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[timestart] 0
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[timestart] 0
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[size] 1600 862
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[size] 1600 862
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[pos] -1 -1
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[pos] -1 -1
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*-41.636795 7980000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-43.418156 1760000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.
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[treeopen] top.principal_tb.
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[treeopen] top.principal_tb.
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[treeopen] top.principal_tb.dut.
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[treeopen] top.principal_tb.dut.
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[treeopen] top.principal_tb.dut.fa.
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[sst_width] 213
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[sst_width] 213
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[signals_width] 198
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[signals_width] 198
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[sst_expanded] 1
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[sst_expanded] 1
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@ -73,8 +72,34 @@ top.principal_tb.dut.left
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top.principal_tb.dut.rightcoder.cha
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top.principal_tb.dut.rightcoder.cha
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[color] 6
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[color] 6
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top.principal_tb.dut.rightcoder.chb
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top.principal_tb.dut.rightcoder.chb
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@8421
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@8420
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[color] 6
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[color] 6
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top.principal_tb.dut.right
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top.principal_tb.dut.right
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@28
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[color] 3
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top.principal_tb.dut.frontcapt.start
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[color] 3
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top.principal_tb.dut.frontcapt.trigger
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[color] 3
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top.principal_tb.dut.frontcapt.echo
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@8420
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[color] 3
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top.principal_tb.dut.frontcapt.distancecounter
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@420
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[color] 3
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top.principal_tb.dut.front
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@28
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[color] 3
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top.principal_tb.dut.backcapt.start
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[color] 3
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top.principal_tb.dut.backcapt.trigger
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[color] 3
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top.principal_tb.dut.backcapt.echo
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@8421
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[color] 3
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top.principal_tb.dut.backcapt.distancecounter
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@420
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[color] 3
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top.principal_tb.dut.back
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[pattern_trace] 1
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[pattern_trace] 1
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[pattern_trace] 0
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[pattern_trace] 0
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@ -10,63 +10,84 @@ entity Principal_tb is
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architecture tb of Principal_tb is
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architecture tb of Principal_tb is
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component Principal
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constant fFpga : INTEGER := 2_000_000;
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port (CLK : in std_logic;
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constant fBaud : INTEGER := 9600;
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BTN : in std_logic;
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IO : inout std_logic_vector (21 downto 16);
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component Principal is
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LED : out std_logic_vector (3 downto 0);
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Generic(
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AN : out std_logic_vector (3 downto 0);
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fFpga : INTEGER := fFpga;
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A_TO_G : out std_logic_vector (6 downto 0);
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fBaud : INTEGER := fBaud
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DOT : out std_logic);
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);
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Port (
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CLK : in std_logic;
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BTN: in std_logic;
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RX: in std_logic;
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TX: out std_logic;
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LEFTCHA: in std_logic;
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LEFTCHB: in std_logic;
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RIGHTCHA: in std_logic;
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RIGHTCHB: in std_logic;
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FRONTTRIGGER: out std_logic;
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FRONTECHO: in std_logic;
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BACKTRIGGER: out std_logic;
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BACKECHO: in std_logic
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);
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end component;
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end component;
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signal CLK : std_logic;
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signal CLK : std_logic;
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signal BTN : std_logic;
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signal BTN : std_logic;
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signal IO : std_logic_vector (21 downto 16);
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signal RX : std_logic;
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signal LED : std_logic_vector (3 downto 0);
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signal TX : std_logic;
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signal AN : std_logic_vector (3 downto 0);
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signal LEFTCHA : std_logic;
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signal A_TO_G : std_logic_vector (6 downto 0);
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signal LEFTCHB : std_logic;
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signal DOT : std_logic;
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signal RIGHTCHA : std_logic;
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signal RIGHTCHB : std_logic;
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signal FRONTTRIGGER : std_logic;
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signal FRONTECHO : std_logic;
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signal BACKTRIGGER : std_logic;
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signal BACKECHO : std_logic;
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constant TbPeriod : time := 20 ns;
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constant TbPeriod : time := 500 ns;
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signal TbClock : std_logic := '0';
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signal TbClock : std_logic := '0';
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signal TbSimEnded : std_logic := '0';
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signal TbSimEnded : std_logic := '0';
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constant BaudPeriod : time := 104167 ns; -- 9600 baud
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signal TbDoneWithCapt : std_logic := '0';
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constant CharacterPeriod : time := 10 * BaudPeriod;
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signal rx : std_logic;
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signal tx : std_logic;
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constant CoderPeriod : time := 27611 ns;
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constant BaudPeriod : time := 1E9 ns / fBaud;
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constant CharacterPeriod : time := 10 * BaudPeriod;
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constant CoderPeriod : time := 27611 ns; -- 10 km/h
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begin
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begin
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dut : Principal
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dut : Principal
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port map (CLK => CLK,
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port map (CLK => CLK,
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BTN => BTN,
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BTN => BTN,
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IO => IO,
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RX => RX,
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LED => LED,
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TX => TX,
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AN => AN,
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LEFTCHA => LEFTCHA,
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A_TO_G => A_TO_G,
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LEFTCHB => LEFTCHB,
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DOT => DOT);
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RIGHTCHA => RIGHTCHA,
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RIGHTCHB => RIGHTCHB,
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FRONTTRIGGER => FRONTTRIGGER,
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FRONTECHO => FRONTECHO,
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BACKTRIGGER => BACKTRIGGER,
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BACKECHO => BACKECHO);
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-- Clock generation
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-- Clock generation
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TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
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TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
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CLK <= TbClock;
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CLK <= TbClock;
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IO(20) <= rx;
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tx <= IO(21);
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leftCoder : process
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leftCoder : process
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begin
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begin
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while TbSimEnded = '0' loop
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while TbSimEnded = '0' loop
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IO(19) <= '1';
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LEFTCHA <= '1';
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wait for CoderPeriod;
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wait for CoderPeriod;
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IO(18) <= '1';
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LEFTCHB <= '1';
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wait for CoderPeriod;
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wait for CoderPeriod;
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IO(19) <= '0';
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LEFTCHA <= '0';
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wait for CoderPeriod;
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wait for CoderPeriod;
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IO(18) <= '0';
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LEFTCHB <= '0';
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wait for CoderPeriod;
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wait for CoderPeriod;
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end loop;
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end loop;
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wait;
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wait;
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@ -75,18 +96,36 @@ begin
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rightCoder : process
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rightCoder : process
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begin
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begin
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while TbSimEnded = '0' loop
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while TbSimEnded = '0' loop
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IO(16) <= '0';
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RIGHTCHA <= '0';
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wait for CoderPeriod;
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wait for CoderPeriod;
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IO(17) <= '0';
|
RIGHTCHB <= '0';
|
||||||
wait for CoderPeriod;
|
wait for CoderPeriod;
|
||||||
IO(16) <= '1';
|
RIGHTCHA <= '1';
|
||||||
wait for CoderPeriod;
|
wait for CoderPeriod;
|
||||||
IO(17) <= '1';
|
RIGHTCHB <= '1';
|
||||||
wait for CoderPeriod;
|
wait for CoderPeriod;
|
||||||
end loop;
|
end loop;
|
||||||
wait;
|
wait;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
|
frontCapt: process
|
||||||
|
begin
|
||||||
|
FRONTECHO <= '0';
|
||||||
|
|
||||||
|
wait on FRONTTRIGGER until FRONTTRIGGER = '1';
|
||||||
|
wait on FRONTTRIGGER until FRONTTRIGGER = '0';
|
||||||
|
|
||||||
|
wait for 10 ms;
|
||||||
|
FRONTECHO <= '1';
|
||||||
|
wait for 15 ms;
|
||||||
|
FRONTECHO <= '0';
|
||||||
|
wait for 35 ms;
|
||||||
|
|
||||||
|
TbDoneWithCapt <= '1';
|
||||||
|
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
|
||||||
stimuli : process
|
stimuli : process
|
||||||
procedure send
|
procedure send
|
||||||
(char : std_logic_vector(7 downto 0)) is
|
(char : std_logic_vector(7 downto 0)) is
|
||||||
|
|
@ -101,7 +140,9 @@ begin
|
||||||
wait for BaudPeriod;
|
wait for BaudPeriod;
|
||||||
end procedure;
|
end procedure;
|
||||||
begin
|
begin
|
||||||
rx <= '1';
|
BTN <= '0';
|
||||||
|
RX <= '1';
|
||||||
|
BACKECHO <= '0';
|
||||||
|
|
||||||
-- Reset generation
|
-- Reset generation
|
||||||
BTN <= '1';
|
BTN <= '1';
|
||||||
|
|
@ -128,22 +169,19 @@ begin
|
||||||
wait for 2 * BaudPeriod;
|
wait for 2 * BaudPeriod;
|
||||||
|
|
||||||
|
|
||||||
-- Send 'C'
|
|
||||||
send(x"43"); -- '?'
|
|
||||||
wait for 5 * CharacterPeriod;
|
|
||||||
|
|
||||||
-- Wait margin
|
|
||||||
wait for 5 * BaudPeriod;
|
|
||||||
|
|
||||||
|
|
||||||
-- Send 'D'
|
-- Send 'D'
|
||||||
send(x"44"); -- '?'
|
send(x"44");
|
||||||
|
wait for 5 * CharacterPeriod;
|
||||||
|
|
||||||
|
wait on TbDoneWithCapt until TbDoneWithCapt = '1';
|
||||||
|
|
||||||
|
-- Send 'C'
|
||||||
|
send(x"43");
|
||||||
wait for 5 * CharacterPeriod;
|
wait for 5 * CharacterPeriod;
|
||||||
|
|
||||||
-- Wait margin
|
-- Wait margin
|
||||||
wait for 5 * BaudPeriod;
|
wait for 5 * BaudPeriod;
|
||||||
|
|
||||||
|
|
||||||
-- Stop the clock and hence terminate the simulation
|
-- Stop the clock and hence terminate the simulation
|
||||||
TbSimEnded <= '1';
|
TbSimEnded <= '1';
|
||||||
wait;
|
wait;
|
||||||
|
|
|
||||||
179
fpga/debug.ucf
179
fpga/debug.ucf
|
|
@ -1,179 +0,0 @@
|
||||||
# __ ____ _ __
|
|
||||||
# / |/ (_)_____________ / | / /___ _ ______ _
|
|
||||||
# / /|_/ / / ___/ ___/ __ \/ |/ / __ \ | / / __ `/
|
|
||||||
# / / / / / /__/ / / /_/ / /| / /_/ / |/ / /_/ /
|
|
||||||
# /_/ /_/_/\___/_/ \____/_/ |_/\____/|___/\__,_/
|
|
||||||
#
|
|
||||||
# Mercury BASEBOARD User Constraints File
|
|
||||||
# Revision 1.0.0 (03/25/2015)
|
|
||||||
# Copyright (c) 2015 MicroNova, LLC
|
|
||||||
# www.micro-nova.com
|
|
||||||
|
|
||||||
# system oscillators
|
|
||||||
NET "EXT_CLK" LOC = "P44" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "CLK" TNM_NET = "CLK";
|
|
||||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
|
|
||||||
|
|
||||||
# PS/2
|
|
||||||
NET "PS2_DATA" LOC = "P13" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PS2_CLK" LOC = "P15" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# Buttons
|
|
||||||
NET "USR_BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BTN<0>" LOC = "P68" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BTN<1>" LOC = "P97" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BTN<2>" LOC = "P7" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BTN<3>" LOC = "P82" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# VGA
|
|
||||||
NET "RED<0>" LOC = "P20" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "RED<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "RED<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "GRN<0>" LOC = "P34" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "GRN<1>" LOC = "P35" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "GRN<2>" LOC = "P36" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BLU<0>" LOC = "P37" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BLU<1>" LOC = "P40" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "HSYNC" LOC = "P16" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "VSYNC" LOC = "P19" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# SWITCHES
|
|
||||||
NET "SW<0>" LOC = "P59" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<1>" LOC = "P60" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<2>" LOC = "P61" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<3>" LOC = "P62" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<4>" LOC = "P64" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<5>" LOC = "P57" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<6>" LOC = "P56" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SW<7>" LOC = "P52" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# 7 SEG
|
|
||||||
NET "AN<0>" LOC = "P50" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "AN<1>" LOC = "P49" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "AN<2>" LOC = "P85" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "AN<3>" LOC = "P84" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<0>" LOC = "P72" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<1>" LOC = "P71" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<2>" LOC = "P70" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<3>" LOC = "P65" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<4>" LOC = "P77" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<5>" LOC = "P78" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "A_TO_G<6>" LOC = "P83" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DOT" LOC = "P73" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# PMOD
|
|
||||||
NET "PMOD<0>" LOC = "P5" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<1>" LOC = "P4" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<2>" LOC = "P6" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<3>" LOC = "P98" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<4>" LOC = "P94" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<5>" LOC = "P93" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<6>" LOC = "P90" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "PMOD<7>" LOC = "P89" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# AUDIO OUT
|
|
||||||
NET "AUDIO_OUT_R" LOC = "P88" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "AUDIO_OUT_L" LOC = "P86" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# memory & bus-switch
|
|
||||||
NET "SWITCH_OEN" LOC = "P3" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "MEMORY_OEN" LOC = "P30" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# flash/usb interface
|
|
||||||
NET "FPGA_CSN" LOC = "P39" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "FLASH_CSN" LOC = "P27" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SPI_MOSI" LOC = "P46" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SPI_MISO" LOC = "P51" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "SPI_SCK" LOC = "P53" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# ADC interface
|
|
||||||
NET "ADC_MISO" LOC = "P21" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "ADC_MOSI" LOC = "P10" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "ADC_SCK" LOC = "P9" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "ADC_CSN" LOC = "P12" | IOSTANDARD = LVTTL ;
|
|
||||||
# __ ____ _ __
|
|
||||||
# / |/ (_)_____________ / | / /___ _ ______ _
|
|
||||||
# / /|_/ / / ___/ ___/ __ \/ |/ / __ \ | / / __ `/
|
|
||||||
# / / / / / /__/ / / /_/ / /| / /_/ / |/ / /_/ /
|
|
||||||
# /_/ /_/_/\___/_/ \____/_/ |_/\____/|___/\__,_/
|
|
||||||
#
|
|
||||||
# Mercury User Constraints File
|
|
||||||
# Revision 1.0.142 (10/24/2012)
|
|
||||||
# Copyright (c) 2012 MicroNova, LLC
|
|
||||||
# www.micro-nova.com
|
|
||||||
|
|
||||||
# user LEDs and button
|
|
||||||
NET "LED<0>" LOC = "P13" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "LED<1>" LOC = "P15" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "LED<2>" LOC = "P16" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "LED<3>" LOC = "P19" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# direct and global-clock I/O
|
|
||||||
NET "DIO<0>" LOC = "P20" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DIO<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DIO<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DIO<3>" LOC = "P34" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DIO<4>" LOC = "P35" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DIO<5>" LOC = "P36" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "DIO<6>" LOC = "P37" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "CIO<0>" LOC = "P40" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "CIO<1>" LOC = "P44" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# in-only pins
|
|
||||||
NET "INPIN<0>" LOC = "P68" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "INPIN<1>" LOC = "P97" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "INPIN<2>" LOC = "P7" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "INPIN<3>" LOC = "P82" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# level-shifted I/O
|
|
||||||
NET "IO<0>" LOC = "P59" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<1>" LOC = "P60" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<2>" LOC = "P61" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<3>" LOC = "P62" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<4>" LOC = "P64" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<5>" LOC = "P57" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<6>" LOC = "P56" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<7>" LOC = "P52" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<8>" LOC = "P50" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<9>" LOC = "P49" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<10>" LOC = "P85" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<11>" LOC = "P84" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<12>" LOC = "P83" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<13>" LOC = "P78" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<14>" LOC = "P77" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<15>" LOC = "P65" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<16>" LOC = "P70" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<17>" LOC = "P71" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<18>" LOC = "P72" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<19>" LOC = "P73" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<20>" LOC = "P5" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<21>" LOC = "P4" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<22>" LOC = "P6" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<23>" LOC = "P98" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<24>" LOC = "P94" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<25>" LOC = "P93" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# memory & bus-switch
|
|
||||||
NET "switch_oen" LOC = "P3" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "memory_oen" LOC = "P30" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# flash/usb interface
|
|
||||||
NET "fpga_csn" LOC = "P39" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "flash_csn" LOC = "P27" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "spi_mosi" LOC = "P46" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "spi_miso" LOC = "P51" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "spi_sck" LOC = "P53" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# ADC interface
|
|
||||||
NET "adc_miso" LOC = "P21" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "adc_mosi" LOC = "P10" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "adc_sck" LOC = "P9" | IOSTANDARD = LVTTL ;
|
|
||||||
NET "adc_csn" LOC = "P12" | IOSTANDARD = LVTTL ;
|
|
||||||
|
|
||||||
# CLOCK timing
|
|
||||||
|
|
@ -1,88 +0,0 @@
|
||||||
LIBRARY ieee;
|
|
||||||
USE ieee.std_logic_1164.all;
|
|
||||||
|
|
||||||
ENTITY hcSr04 IS
|
|
||||||
GENERIC(
|
|
||||||
fFpga : INTEGER := 50_000_000 -- frequency of the FPGA clock (Hz)
|
|
||||||
);
|
|
||||||
PORT(
|
|
||||||
clk : IN STD_LOGIC; -- clock of the FPGA
|
|
||||||
echo : IN STD_LOGIC; -- echo pin of the hcSr04
|
|
||||||
distance : OUT INTEGER RANGE 0 TO 65535; -- Divide by 58 to get the value in cm
|
|
||||||
trigger : OUT STD_LOGIC; -- trigger pin of the hcSr04
|
|
||||||
start : IN STD_LOGIC; -- Set to '1' everytime a measurement is needed (or keep at '1' for continuous measurement)
|
|
||||||
finished : OUT STD_LOGIC -- Driven to '1' everytime a measurement has finished
|
|
||||||
);
|
|
||||||
END hcSr04;
|
|
||||||
|
|
||||||
ARCHITECTURE Behavioral OF hcSr04 IS
|
|
||||||
-- Generate us clock
|
|
||||||
CONSTANT fUs : INTEGER := 1_000_000; -- Frequency of the microsecond clock
|
|
||||||
CONSTANT usTicks : INTEGER := fFPGA / fUs; -- Number of FPGA tick that makes a microsecond
|
|
||||||
SIGNAL fpgaCounter : INTEGER RANGE 0 TO usTicks - 1; -- Count the microsecond
|
|
||||||
SIGNAL usClk : STD_LOGIC; -- Clock that ticks every us
|
|
||||||
|
|
||||||
-- Trigger
|
|
||||||
CONSTANT triggerDuration : INTEGER := 10; -- Number of us that makes up a trigger sequence
|
|
||||||
SIGNAL triggerCounter : INTEGER RANGE 0 TO triggerDuration - 1 := 0; -- Progress in the trigger sequence
|
|
||||||
SIGNAL theTrigger : STD_LOGIC := '0'; -- Trigger pin but with default value
|
|
||||||
|
|
||||||
-- Measurement
|
|
||||||
CONSTANT measurementDuration : INTEGER := 60_000; -- Number of us that makes up a measurement cycle
|
|
||||||
SIGNAL measurementCounter : INTEGER RANGE 0 TO measurementDuration - 1 := 0; -- Progress in the measurement cycle
|
|
||||||
|
|
||||||
-- Distance
|
|
||||||
SIGNAL distanceCounter : INTEGER RANGE 0 TO 65535 := 0; -- Distance measured (in us)
|
|
||||||
|
|
||||||
-- State machine
|
|
||||||
TYPE stateType IS (waiting, triggering, measuring);
|
|
||||||
SIGNAL state : stateType;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
us : process(clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(clk) then
|
|
||||||
if fpgaCounter = 0 then
|
|
||||||
usClk <= '0';
|
|
||||||
elsif fpgaCounter = 1 then
|
|
||||||
usClk <= '1';
|
|
||||||
end if;
|
|
||||||
fpgaCounter <= fpgaCounter + 1;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
trigger <= theTrigger;
|
|
||||||
|
|
||||||
measure : process(usClk)
|
|
||||||
begin
|
|
||||||
if rising_edge(usClk) then
|
|
||||||
CASE state IS
|
|
||||||
WHEN waiting =>
|
|
||||||
finished <= '0';
|
|
||||||
IF start = '1' THEN
|
|
||||||
theTrigger <= '1';
|
|
||||||
triggerCounter <= 0;
|
|
||||||
state <= triggering;
|
|
||||||
END IF;
|
|
||||||
WHEN triggering =>
|
|
||||||
triggerCounter <= triggerCounter + 1;
|
|
||||||
IF triggerCounter = triggerDuration - 1 THEN
|
|
||||||
theTrigger <= '0';
|
|
||||||
measurementCounter <= 0;
|
|
||||||
distanceCounter <= 0;
|
|
||||||
state <= measuring;
|
|
||||||
END IF;
|
|
||||||
WHEN measuring =>
|
|
||||||
IF echo = '1' and distanceCounter < 65535 THEN
|
|
||||||
distanceCounter <= distanceCounter + 1;
|
|
||||||
END IF;
|
|
||||||
measurementCounter <= measurementCounter + 1;
|
|
||||||
IF measurementCounter = measurementDuration - 1 THEN
|
|
||||||
distance <= distanceCounter;
|
|
||||||
finished <= '1';
|
|
||||||
state <= waiting;
|
|
||||||
END IF;
|
|
||||||
END CASE;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
END Behavioral;
|
|
||||||
106
fpga/hcsr04.vhd
Normal file
106
fpga/hcsr04.vhd
Normal file
|
|
@ -0,0 +1,106 @@
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
ENTITY hcsr04 IS
|
||||||
|
GENERIC(
|
||||||
|
fFpga : INTEGER := 50_000_000 -- frequency of the FPGA clock (Hz)
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
clk : IN STD_LOGIC; -- clock of the FPGA
|
||||||
|
reset : IN STD_LOGIC; -- hard reset
|
||||||
|
echo : IN STD_LOGIC; -- echo pin of the hcsr04
|
||||||
|
distance : OUT INTEGER; -- Divide by 58 to get the value in cm
|
||||||
|
trigger : OUT STD_LOGIC; -- trigger pin of the hcsr04
|
||||||
|
start : IN STD_LOGIC; -- Set to '1' everytime a measurement is needed (or keep at '1' for continuous measurement)
|
||||||
|
finished : OUT STD_LOGIC -- Driven to '1' everytime a measurement has finished
|
||||||
|
);
|
||||||
|
END hcsr04;
|
||||||
|
|
||||||
|
ARCHITECTURE Behavioral OF hcsr04 IS
|
||||||
|
-- Generate us clock
|
||||||
|
CONSTANT fUs : INTEGER := 1_000_000; -- Frequency of the microsecond clock
|
||||||
|
CONSTANT usTicks : INTEGER := fFPGA / fUs / 2; -- Number of FPGA tick that makes a demi-microsecond
|
||||||
|
SIGNAL fpgaCounter : INTEGER; -- Count the microsecond
|
||||||
|
SIGNAL usClk : STD_LOGIC := '0'; -- Clock that ticks every us
|
||||||
|
|
||||||
|
-- Trigger
|
||||||
|
CONSTANT triggerDuration : INTEGER := 10; -- Number of us that makes up a trigger sequence
|
||||||
|
SIGNAL triggerCounter : INTEGER; -- Progress in the trigger sequence
|
||||||
|
SIGNAL theTrigger : STD_LOGIC := '0'; -- Trigger pin but with default value
|
||||||
|
|
||||||
|
-- Measurement
|
||||||
|
CONSTANT measurementDuration : INTEGER := 60_000; -- Number of us that makes up a measurement cycle
|
||||||
|
SIGNAL measurementCounter : INTEGER := 0; -- Progress in the measurement cycle
|
||||||
|
|
||||||
|
-- Distance
|
||||||
|
CONSTANT maxDistance : INTEGER := 29000; -- 5m
|
||||||
|
SIGNAL distanceCounter : INTEGER := 0; -- Distance measured (in us)
|
||||||
|
|
||||||
|
-- State machine
|
||||||
|
TYPE stateType IS (waiting, triggering, measuring);
|
||||||
|
SIGNAL state : stateType;
|
||||||
|
SIGNAL startUs : STD_LOGIC := '0'; -- A propagation of the start signal
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
us : process(clk, reset)
|
||||||
|
begin
|
||||||
|
if reset = '1' then
|
||||||
|
usClk <= '0';
|
||||||
|
fpgaCounter <= 0;
|
||||||
|
startUs <= '0';
|
||||||
|
elsif rising_edge(clk) then
|
||||||
|
|
||||||
|
if start = '1' then
|
||||||
|
startUs <= '1';
|
||||||
|
elsif state /= waiting then
|
||||||
|
startUs <= '0';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
if fpgaCounter >= usTicks - 1 then
|
||||||
|
fpgaCounter <= 0;
|
||||||
|
usClk <= not usClk;
|
||||||
|
else
|
||||||
|
fpgaCounter <= fpgaCounter + 1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
trigger <= theTrigger;
|
||||||
|
|
||||||
|
measure : process(usClk, reset)
|
||||||
|
begin
|
||||||
|
if reset = '1' then
|
||||||
|
state <= waiting;
|
||||||
|
finished <= '0';
|
||||||
|
distance <= 0;
|
||||||
|
elsif rising_edge(usClk) then
|
||||||
|
CASE state IS
|
||||||
|
WHEN waiting =>
|
||||||
|
finished <= '0';
|
||||||
|
IF startUs = '1' THEN
|
||||||
|
theTrigger <= '1';
|
||||||
|
triggerCounter <= 0;
|
||||||
|
state <= triggering;
|
||||||
|
END IF;
|
||||||
|
WHEN triggering =>
|
||||||
|
triggerCounter <= triggerCounter + 1;
|
||||||
|
IF triggerCounter >= triggerDuration - 1 THEN
|
||||||
|
theTrigger <= '0';
|
||||||
|
measurementCounter <= 0;
|
||||||
|
distanceCounter <= 0;
|
||||||
|
state <= measuring;
|
||||||
|
END IF;
|
||||||
|
WHEN measuring =>
|
||||||
|
IF echo = '1' and distanceCounter < maxDistance THEN
|
||||||
|
distanceCounter <= distanceCounter + 1;
|
||||||
|
END IF;
|
||||||
|
measurementCounter <= measurementCounter + 1;
|
||||||
|
IF measurementCounter >= measurementDuration - 1 THEN
|
||||||
|
distance <= distanceCounter;
|
||||||
|
finished <= '1';
|
||||||
|
state <= waiting;
|
||||||
|
END IF;
|
||||||
|
END CASE;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
END Behavioral;
|
||||||
48
fpga/hcsr04_tb.gtkw
Normal file
48
fpga/hcsr04_tb.gtkw
Normal file
|
|
@ -0,0 +1,48 @@
|
||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
|
||||||
|
[*] Tue Feb 27 14:49:24 2018
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hcsr04_tb.ghw"
|
||||||
|
[dumpfile_mtime] "Tue Feb 27 14:48:30 2018"
|
||||||
|
[dumpfile_size] 5884923
|
||||||
|
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/hcsr04_tb.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1600 862
|
||||||
|
[pos] -1 -1
|
||||||
|
*-44.256817 34900000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[treeopen] top.
|
||||||
|
[treeopen] top.hcsr04_tb.
|
||||||
|
[sst_width] 213
|
||||||
|
[signals_width] 174
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 243
|
||||||
|
@28
|
||||||
|
top.hcsr04_tb.dut.clk
|
||||||
|
top.hcsr04_tb.dut.reset
|
||||||
|
@8420
|
||||||
|
top.hcsr04_tb.dut.fpgacounter
|
||||||
|
@28
|
||||||
|
top.hcsr04_tb.dut.usclk
|
||||||
|
[color] 5
|
||||||
|
top.hcsr04_tb.dut.start
|
||||||
|
[color] 2
|
||||||
|
top.hcsr04_tb.dut.startus
|
||||||
|
[color] 1
|
||||||
|
top.hcsr04_tb.dut.trigger
|
||||||
|
@8420
|
||||||
|
[color] 2
|
||||||
|
top.hcsr04_tb.dut.measurementcounter
|
||||||
|
@28
|
||||||
|
[color] 1
|
||||||
|
top.hcsr04_tb.dut.echo
|
||||||
|
@8420
|
||||||
|
[color] 2
|
||||||
|
top.hcsr04_tb.dut.distancecounter
|
||||||
|
@28
|
||||||
|
[color] 5
|
||||||
|
top.hcsr04_tb.dut.finished
|
||||||
|
@420
|
||||||
|
[color] 5
|
||||||
|
top.hcsr04_tb.distance
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
||||||
115
fpga/hcsr04_tb.vhd
Normal file
115
fpga/hcsr04_tb.vhd
Normal file
|
|
@ -0,0 +1,115 @@
|
||||||
|
-- Testbench automatically generated online
|
||||||
|
-- at http://vhdl.lapinoo.net
|
||||||
|
-- Generation date : 27.2.2018 12:52:54 GMT
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity hcsr04_tb is
|
||||||
|
end hcsr04_tb;
|
||||||
|
|
||||||
|
architecture tb of hcsr04_tb is
|
||||||
|
|
||||||
|
component hcSr04
|
||||||
|
generic (
|
||||||
|
fFpga : INTEGER := 2_000_000 -- Reduce speed to increase simulation speed
|
||||||
|
);
|
||||||
|
port (
|
||||||
|
clk : in std_logic;
|
||||||
|
reset : in std_logic;
|
||||||
|
echo : in std_logic;
|
||||||
|
distance : out integer;
|
||||||
|
trigger : out std_logic;
|
||||||
|
start : in std_logic;
|
||||||
|
finished : out std_logic
|
||||||
|
);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal clk : std_logic;
|
||||||
|
signal reset : std_logic;
|
||||||
|
signal echo : std_logic;
|
||||||
|
signal distance : integer;
|
||||||
|
signal trigger : std_logic;
|
||||||
|
signal start : std_logic;
|
||||||
|
signal finished : std_logic;
|
||||||
|
|
||||||
|
constant TbPeriod : time := 500 ns;
|
||||||
|
signal TbClock : std_logic := '0';
|
||||||
|
signal TbSimEnded : std_logic := '0';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
dut : hcSr04 port map (clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
echo => echo,
|
||||||
|
distance => distance,
|
||||||
|
trigger => trigger,
|
||||||
|
start => start,
|
||||||
|
finished => finished);
|
||||||
|
|
||||||
|
-- Clock generation
|
||||||
|
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
|
||||||
|
|
||||||
|
clk <= TbClock;
|
||||||
|
|
||||||
|
stimuli : process
|
||||||
|
variable startT : time;
|
||||||
|
variable stopT : time;
|
||||||
|
variable delta : time;
|
||||||
|
begin
|
||||||
|
echo <= '0';
|
||||||
|
start <= '0';
|
||||||
|
|
||||||
|
-- Reset generation
|
||||||
|
reset <= '1';
|
||||||
|
wait for 100 ns;
|
||||||
|
reset <= '0';
|
||||||
|
wait for 100 ns;
|
||||||
|
|
||||||
|
|
||||||
|
report "TEST First measurement" severity note;
|
||||||
|
startT := now;
|
||||||
|
start <= '1';
|
||||||
|
wait for TbPeriod;
|
||||||
|
start <= '0';
|
||||||
|
|
||||||
|
wait for 19 ms;
|
||||||
|
echo <= '1';
|
||||||
|
wait for 15 ms;
|
||||||
|
echo <= '0';
|
||||||
|
|
||||||
|
wait on finished until finished = '1';
|
||||||
|
stopT := now;
|
||||||
|
|
||||||
|
delta := stopT - startT;
|
||||||
|
report "Measurement took " & time'image(now);
|
||||||
|
|
||||||
|
assert distance = 15000 report "Wrong distance reported" severity error;
|
||||||
|
|
||||||
|
wait for 5 ms; -- Margin
|
||||||
|
|
||||||
|
|
||||||
|
report "TEST Second measurement" severity note;
|
||||||
|
startT := now;
|
||||||
|
start <= '1';
|
||||||
|
wait for TbPeriod;
|
||||||
|
start <= '0';
|
||||||
|
|
||||||
|
|
||||||
|
wait on finished until finished = '1';
|
||||||
|
stopT := now;
|
||||||
|
|
||||||
|
delta := stopT - startT;
|
||||||
|
report "Measurement took " & time'image(now);
|
||||||
|
|
||||||
|
assert distance = 0 report "Wrong distance reported" severity error;
|
||||||
|
|
||||||
|
wait for 5 ms; -- Margin
|
||||||
|
|
||||||
|
|
||||||
|
-- Stop the clock and hence terminate the simulation
|
||||||
|
TbSimEnded <= '1';
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end tb;
|
||||||
38
fpga/principal.ucf
Normal file
38
fpga/principal.ucf
Normal file
|
|
@ -0,0 +1,38 @@
|
||||||
|
# CLK
|
||||||
|
NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
|
||||||
|
NET "CLK" TNM_NET = "CLK";
|
||||||
|
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
|
||||||
|
|
||||||
|
|
||||||
|
# BTN
|
||||||
|
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<0>
|
||||||
|
NET "RX" LOC = "P59" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<1>
|
||||||
|
NET "TX" LOC = "P60" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<2>
|
||||||
|
NET "LEFTCHA" LOC = "P61" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<3>
|
||||||
|
NET "LEFTCHB" LOC = "P62" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<4>
|
||||||
|
NET "RIGHTCHA" LOC = "P64" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<5>
|
||||||
|
NET "RIGHTCHB" LOC = "P57" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<6>
|
||||||
|
NET "FRONTTRIGGER" LOC = "P56" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<7>
|
||||||
|
NET "FRONTECHO" LOC = "P52" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<8>
|
||||||
|
NET "BACKTRIGGER" LOC = "P50" | IOSTANDARD = LVTTL ;
|
||||||
|
|
||||||
|
# IO<9>
|
||||||
|
NET "BACKECHO" LOC = "P49" | IOSTANDARD = LVTTL ;
|
||||||
|
|
@ -5,15 +5,5 @@ PROGRAMMER = mercpcl
|
||||||
|
|
||||||
TOPLEVEL = Principal
|
TOPLEVEL = Principal
|
||||||
# Prod
|
# Prod
|
||||||
# VHDSOURCE = $(TOPLEVEL).vhd uart.vhd
|
VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd
|
||||||
# CONSTRAINTS = mercury.ucf
|
CONSTRAINTS = principal.ucf
|
||||||
# Debug
|
|
||||||
VHDSOURCE = $(TOPLEVEL).vhd $(filter-out %_tb.vhd,$(wildcard *.vhd))
|
|
||||||
CONSTRAINTS = debug.ucf
|
|
||||||
|
|
||||||
|
|
||||||
# Implement design
|
|
||||||
# Allow unmatched LOC Constraints
|
|
||||||
NGDBUILD_OPTS += -aul
|
|
||||||
# Allow unmatched Timing Group Constraints
|
|
||||||
NGDBUILD_OPTS += -aut
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue