geoffrey/cdf2018-principal
geoffrey/cdf2018-principal
1
0
Fork 0
mirror of https://github.com/RobotechLille/cdf2018-principal synced 2024-11-14 20:36:03 +01:00
Code Issues Releases Wiki Activity

Broche de référence pour PWM

Browse source
This commit is contained in:
Geoffrey Frogeye 2018-05-09 01:00:40 +02:00
parent 289898a763
commit dad788c3a4
2 changed files with 16 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
fpga/Principal.vhd
View file

@ -21,9 +21,11 @@ entity Principal is
FRONTECHO: in std_logic; FRONTECHO: in std_logic;
BACKTRIGGER: out std_logic; BACKTRIGGER: out std_logic;
BACKECHO: in std_logic; BACKECHO: in std_logic;
ENAREF: out std_logic;
ENA: out std_logic; ENA: out std_logic;
IN1ENC: out std_logic; IN1ENC: out std_logic;
IN2: out std_logic; IN2: out std_logic;
ENBREF: out std_logic;
ENB: out std_logic; ENB: out std_logic;
IN3END: out std_logic; IN3END: out std_logic;
IN4: out std_logic IN4: out std_logic
@ -225,6 +227,7 @@ begin
data => enAd, data => enAd,
pulse => ENA pulse => ENA
); );
ENAREF <= '1';
in1enCp : PWM port map ( in1enCp : PWM port map (
clk => pwmClk, clk => pwmClk,
@ -238,6 +241,7 @@ begin
data => enBd, data => enBd,
pulse => ENB pulse => ENB
); );
ENBREF <= '1';
in3enDp : PWM port map ( in3enDp : PWM port map (
clk => pwmClk, clk => pwmClk,

20
fpga/principal.ucf
View file

@ -38,24 +38,28 @@ NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ;
NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ; NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ;
# IO<20> # IO<20>
NET "ENA" LOC = "P5" | IOSTANDARD = LVTTL ; NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ;
# IO<21> # IO<21>
NET "IN1ENC" LOC = "P4" | IOSTANDARD = LVTTL ; NET "ENA" LOC = "P4" | IOSTANDARD = LVTTL ;
# IO<22> # IO<22>
NET "IN2" LOC = "P6" | IOSTANDARD = LVTTL ; NET "IN1ENC" LOC = "P6" | IOSTANDARD = LVTTL ;
# IO<23> # IO<23>
NET "ENB" LOC = "P98" | IOSTANDARD = LVTTL ; NET "IN2" LOC = "P98" | IOSTANDARD = LVTTL ;
# IO<24> # IO<24>
NET "IN3END" LOC = "P94" | IOSTANDARD = LVTTL ; NET "ENBREF" LOC = "P94" | IOSTANDARD = LVTTL ;
# IO<25> # IO<25>
NET "IN4" LOC = "P93" | IOSTANDARD = LVTTL ; NET "ENB" LOC = "P93" | IOSTANDARD = LVTTL ;
# IO<26>
NET "IN3END" LOC = "P90" | IOSTANDARD = LVTTL ;
# IO<27>
NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ;
# NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
# NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
# NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ; # NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
# NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ; # NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;