Fix codeuses

fpga/hedm.vhd

@@ -1,9 +1,6 @@
 -- Process signals from HEDM-550X encoder
 -- and output the value read
 
--- TODO Quelques modifications apportées depuis test avec les vraies codeuses
--- un nouveau test sera nécessaire (vérifier notamment le sens de parcours)
-
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.numeric_std.all;
@@ -20,59 +17,63 @@ entity hedm is
 end hedm;
 
 architecture Behavioral of hedm is
+    signal counter : integer := 0;
+    signal oldCounter : integer := 0;
+    signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
     signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
 begin
     processInput : process(clk, reset)
-        variable counter : integer := 0;
     begin
         if reset = '1' then
-            counter := 0;
-            counts <= 0;
+            counter <= 0;
+            An <= '0';
+            Bn <= '0';
             Ap <= '0';
             Bp <= '0';
         elsif rising_edge(clk) then
 
-            if zero = '1' then
-                counter := 0;
-            end if;
+            Ap <= An;
+            Bp <= Bn;
+
+            An <= chA;
+            Bn <= chB;
 
             -- On pourrait optimiser la logique avec un tableau de Karnaugh ou autres méthodes
             -- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
             -- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
 
-            if (Ap = '0' and chA = '1') then -- Front montant A
-                if (chB = '0') then
-                    counter := counter + 1;
+            if (Ap = '0' and An = '1') then -- Front montant A
+                if (Bn = '0') then
+                    counter <= oldCounter + 1;
                 else
-                    counter := counter - 1;
+                    counter <= oldCounter - 1;
                 end if;
-            elsif (Ap = '1' and chA = '0') then -- Front descendant A
-                if (chB = '1') then
-                    counter := counter + 1;
+            elsif (Ap = '1' and An = '0') then -- Front descendant A
+                if (Bn = '1') then
+                    counter <= oldCounter + 1;
                 else
-                    counter := counter - 1;
+                    counter <= oldCounter - 1;
                 end if;
-            elsif (Bp = '0' and chB = '1') then -- Front montant B
-                if (chA = '1') then
-                    counter := counter + 1;
+            elsif (Bp = '0' and Bn = '1') then -- Front montant B
+                if (An = '1') then
+                    counter <= oldCounter + 1;
                 else
-                    counter := counter - 1;
+                    counter <= oldCounter - 1;
                 end if;
-            elsif (Bp = '1' and chB = '0') then -- Front descendant B
-                if (chA = '0') then
-                    counter := counter + 1;
+            elsif (Bp = '1' and Bn = '0') then -- Front descendant B
+                if (An = '0') then
+                    counter <= oldCounter + 1;
                 else
-                    counter := counter - 1;
+                    counter <= oldCounter - 1;
                 end if;
+            else
+                counter <= oldCounter;
             end if;
-
-            Ap <= chA;
-            Bp <= chB;
-
-            counts <= counter;
-
         end if;
     end process;
 
+    oldCounter <= 0 when zero = '1' else counter;
+    counts <= counter;
+
 end Behavioral;
 

fpga/hedm_tb.gtkw

@@ -1,10 +1,10 @@
 [*]
-[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Tue Feb 27 08:32:01 2018
+[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI
+[*] Sat May  5 22:58:30 2018
 [*]
 [dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.ghw"
-[dumpfile_mtime] "Tue Feb 27 08:31:12 2018"
-[dumpfile_size] 4287
+[dumpfile_mtime] "Sat May  5 22:57:01 2018"
+[dumpfile_size] 5011
 [savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/hedm_tb.gtkw"
 [timestart] 0
 [size] 1600 862
@@ -13,7 +13,7 @@
 [treeopen] top.
 [treeopen] top.hedm_tb.
 [sst_width] 213
-[signals_width] 78
+[signals_width] 110
 [sst_expanded] 1
 [sst_vpaned_height] 244
 @28
@@ -33,10 +33,13 @@ top.hedm_tb.dut.bp
 top.hedm_tb.dut.an
 [color] 2
 top.hedm_tb.dut.bn
+@421
+[color] 7
+top.hedm_tb.dut.oldcounter
 @420
 [color] 1
 top.hedm_tb.dut.counts
-@8421
+@8420
 [color] 1
 top.hedm_tb.dut.counts
 [pattern_trace] 1

fpga/hedm_tb.vhd

@@ -112,7 +112,7 @@ begin
         wait for TbPeriod;
 
         wait for 5 * TbPeriod;
-        assert counts = 2 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
+        assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
 
         zero <= '1';
         wait for TbPeriod;