From f730d7b2b11a9252609379956d55a427b03af412 Mon Sep 17 00:00:00 2001 From: Geoffrey Frogeye Date: Thu, 10 May 2018 10:09:56 +0200 Subject: [PATCH] =?UTF-8?q?Ajout=20de=20deux=20capteurs=20=C3=A0=20ultraso?= =?UTF-8?q?ns?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- fpga/Principal.vhd | 100 +++++++++++++++++++++++++++++++++------------ fpga/principal.ucf | 11 +++-- 2 files changed, 81 insertions(+), 30 deletions(-) diff --git a/fpga/Principal.vhd b/fpga/Principal.vhd index 4895b42..3f4f35b 100644 --- a/fpga/Principal.vhd +++ b/fpga/Principal.vhd @@ -18,9 +18,11 @@ entity Principal is RIGHTCHA: in std_logic; RIGHTCHB: in std_logic; FRONTTRIGGER: out std_logic; - FRONTECHO: in std_logic; BACKTRIGGER: out std_logic; - BACKECHO: in std_logic; + FRONTLECHO: in std_logic; + BACKLECHO: in std_logic; + FRONTRECHO: in std_logic; + BACKRECHO: in std_logic; ENAREF: out std_logic; ENA: out std_logic; IN1ENC: out std_logic; @@ -53,12 +55,20 @@ architecture Behavioral of Principal is end component; -- Distance sensors - signal front : integer := 0; - signal frontRaw : integer := 0; - signal frontFinished : std_logic; - signal back : integer := 0; - signal backRaw : integer := 0; - signal backFinished : std_logic; + signal frontMin : integer := 0; + signal backMin : integer := 0; + signal frontL : integer := 0; + signal frontLRaw : integer := 0; + signal frontLFinished : std_logic; + signal backL : integer := 0; + signal backLRaw : integer := 0; + signal backLFinished : std_logic; + signal frontR : integer := 0; + signal frontRRaw : integer := 0; + signal frontRFinished : std_logic; + signal backR : integer := 0; + signal backRRaw : integer := 0; + signal backRFinished : std_logic; component hcsr04 IS generic( fFpga : INTEGER := fFpga @@ -187,39 +197,74 @@ begin counts => right ); - frontCapt: hcsr04 port map ( + frontLCapt: hcsr04 port map ( clk => CLK, reset => reset, - echo => FRONTECHO, - distance => frontRaw, + echo => FRONTLECHO, + distance => frontLRaw, trigger => FRONTTRIGGER, start => '1', - finished => frontFinished + finished => frontLFinished ); - frontFilter : FIR port map ( + frontLFilter : FIR port map ( clock => CLK, reset => reset, - signalIn => frontRaw, - signalOut => front, - start => frontFinished + signalIn => frontLRaw, + signalOut => frontL, + start => frontLFinished -- done => done ); - backCapt: hcsr04 port map ( + frontRCapt: hcsr04 port map ( + clk => CLK, + reset => reset, + echo => FRONTRECHO, + distance => frontRRaw, + -- trigger => FRONTTRIGGER, + start => '1', + finished => frontRFinished + ); + frontRFilter : FIR port map ( + clock => CLK, + reset => reset, + signalIn => frontRRaw, + signalOut => frontR, + start => frontRFinished + -- done => done + ); + + backLCapt: hcsr04 port map ( clk => CLK, reset => reset, - echo => BACKECHO, - distance => backRaw, + echo => BACKLECHO, + distance => backLRaw, trigger => BACKTRIGGER, start => '1', - finished => backFinished + finished => backLFinished ); - backFilter : FIR port map ( + backLFilter : FIR port map ( clock => CLK, reset => reset, - signalIn => backRaw, - signalOut => back, - start => backFinished + signalIn => backLRaw, + signalOut => backL, + start => backLFinished + -- done => done + ); + backRCapt: hcsr04 port map ( + clk => CLK, + reset => reset, + echo => BACKRECHO, + distance => backRRaw, + -- trigger => BACKTRIGGER, + start => '1', + finished => backRFinished + ); + backRFilter : FIR port map ( + clock => CLK, + reset => reset, + signalIn => backRRaw, + signalOut => backR, + start => backRFinished -- done => done ); enAp : PWM port map ( @@ -263,14 +308,17 @@ begin rx => RX ); + frontMin <= frontLRaw when frontLRaw < frontRRaw else frontRRaw; + backMin <= backLRaw when backLRaw < backRRaw else backRRaw; + com: communication port map( clock => CLK, reset => reset, left => left, right => right, zerocoder => zerocoder, - front => front, - back => back, + front => frontMin, + back => backMin, txData => txData, txStb => txStb, txAck => txAck, diff --git a/fpga/principal.ucf b/fpga/principal.ucf index 0f02f8a..f1d6fc9 100644 --- a/fpga/principal.ucf +++ b/fpga/principal.ucf @@ -29,13 +29,13 @@ NET "RIGHTCHB" LOC = "P65" | IOSTANDARD = LVTTL ; NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ; # IO<17> -NET "FRONTECHO" LOC = "P71" | IOSTANDARD = LVTTL ; +NET "FRONTLECHO" LOC = "P71" | IOSTANDARD = LVTTL ; # IO<18> NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ; # IO<19> -NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ; +NET "BACKLECHO" LOC = "P73" | IOSTANDARD = LVTTL ; # IO<20> NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ; @@ -61,5 +61,8 @@ NET "IN3END" LOC = "P90" | IOSTANDARD = LVTTL ; # IO<27> NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ; -# NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ; -# NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ; +# IO<28> + NET "FRONTRECHO" LOC = "P88" | IOSTANDARD = LVTTL ; + +# IO<29> + NET "BACKRECHO" LOC = "P86" | IOSTANDARD = LVTTL ;