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31 lines
665 B
VHDL
31 lines
665 B
VHDL
-- Inspiré de http://www.fpga4fun.com/PWM_DAC_2.html
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.ALL;
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entity PWM is
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port (
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clk : in std_logic;
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data : in std_logic_vector (7 downto 0) := "00000000";
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pulse : out std_logic
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);
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end PWM;
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architecture Behavioral of PWM is
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signal accuI : integer := 0;
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signal dataI : integer := 0;
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begin
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dataI <= to_integer(unsigned(data));
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process(clk, data)
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begin
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if rising_edge(clk) then
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accuI <= accuI mod 256 + dataI;
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end if;
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end process;
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pulse <= '1' when accuI > 256 else '0';
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end Behavioral;
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