mirror of
https://github.com/RobotechLille/cdf2018-principal
synced 2024-06-02 19:15:00 +02:00
156 lines
5 KiB
VHDL
156 lines
5 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity Principal is
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Port ( CLK : in STD_LOGIC; -- Clock
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BTN : in STD_LOGIC; -- Reset
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-- FA
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IO : inout STD_LOGIC_VECTOR (21 downto 20);
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-- Debug
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LED : out STD_LOGIC_VECTOR (3 downto 0);
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AN : out STD_LOGIC_VECTOR (3 downto 0);
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A_TO_G : out STD_LOGIC_VECTOR (6 downto 0);
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DOT : out STD_LOGIC
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);
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end Principal;
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architecture Behavioral of Principal is
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-- Blink led
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signal count : integer := 0;
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signal theled: std_logic_vector(3 downto 0) := "0000";
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-- General
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signal reset : std_logic := '0';
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-- Encoder
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signal left : integer;
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signal right : integer;
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-- Sensors
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signal front : integer;
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signal back : integer;
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-- AF
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component uart is
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generic (
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baud : positive := 9600;
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clock_frequency : positive := 50_000_000
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);
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port (
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clock : in std_logic;
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reset : in std_logic;
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data_stream_in : in std_logic_vector(7 downto 0);
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data_stream_in_stb : in std_logic;
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data_stream_in_ack : out std_logic;
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data_stream_out : out std_logic_vector(7 downto 0);
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data_stream_out_stb : out std_logic;
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tx : out std_logic;
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rx : in std_logic
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);
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end component;
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constant BAUD_COUNT: std_logic_vector := x"1458"; -- 96000 Baud at 50 MHz
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signal txData : std_logic_vector(7 downto 0);
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signal txStb : std_logic := '0';
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signal txAck : std_logic := '0';
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signal rxData : std_logic_vector(7 downto 0);
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signal rxStb : std_logic := '0';
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-- Handling
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component communication is
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Port (
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clock : in std_logic;
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reset : in std_logic;
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left : in integer;
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right : in integer;
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front : in integer;
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back : in integer;
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txData : out std_logic_vector(7 downto 0);
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txStb : out std_logic;
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txAck : in std_logic;
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rxData : in std_logic_vector(7 downto 0);
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rxStb : in std_logic
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);
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end component;
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-- Debug
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component sevenseg is
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Port (
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data : in STD_LOGIC_VECTOR (15 downto 0);
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clock : in STD_LOGIC;
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anode : out STD_LOGIC_VECTOR (3 downto 0);
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segment : out STD_LOGIC_VECTOR (6 downto 0);
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dot : out STD_LOGIC
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);
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end component;
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signal sevensegdata: std_logic_vector(15 downto 0);
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signal fullseg: std_logic_vector(7 downto 0);
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begin
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reset <= BTN;
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FA: uart port map(
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clock => CLK,
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reset => reset,
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data_stream_in => txData,
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data_stream_in_stb => txStb,
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data_stream_in_ack => txAck,
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data_stream_out => rxData,
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data_stream_out_stb => rxStb,
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tx => IO(21),
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rx => IO(20)
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);
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com: communication port map(
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clock => CLK,
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reset => reset,
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left => left,
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right => right,
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front => front,
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back => back,
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txData => txData,
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txStb => txStb,
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txAck => txAck,
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rxData => rxData,
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rxStb => rxStb
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);
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-- Debug
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blinkled : process(CLK, reset)
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begin
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if reset = '1' then
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count <= 0;
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theled <= "0000";
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elsif CLK'event and CLK = '1' then
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if count = 9999999 then
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count <= 0;
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theled(3) <= not theled(3);
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theled(2 downto 0) <= "000";
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else
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count <= count + 1;
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theled(2 downto 0) <= theled(2 downto 0) or (txStb & rxStb & txAck);
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end if;
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end if;
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end process;
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LED <= theled;
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debugSeg: sevenseg port map(
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data => sevensegdata,
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clock => CLK,
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anode => AN,
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segment => A_TO_G,
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dot => DOT
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);
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sevensegdata(15 downto 8) <= rxData;
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sevensegdata(7 downto 0) <= txData;
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end Behavioral;
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