cdf2018-principal/fpga/principal.ucf

# CLK
NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;


# BTN
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;

# IO<0>
NET "RX" LOC = "P59" | IOSTANDARD = LVTTL ;

# IO<1>
NET "TX" LOC = "P60" | IOSTANDARD = LVTTL ;

# IO<2>
NET "LEFTCHA" LOC = "P61" | IOSTANDARD = LVTTL ;

# IO<3>
NET "LEFTCHB" LOC = "P62" | IOSTANDARD = LVTTL ;

# IO<4>
NET "RIGHTCHA" LOC = "P64" | IOSTANDARD = LVTTL ;

# IO<5>
NET "RIGHTCHB" LOC = "P57" | IOSTANDARD = LVTTL ;

# IO<6>
NET "FRONTTRIGGER" LOC = "P56" | IOSTANDARD = LVTTL ;

# IO<7>
NET "FRONTECHO" LOC = "P52" | IOSTANDARD = LVTTL ;

# IO<8>
NET "BACKTRIGGER" LOC = "P50" | IOSTANDARD = LVTTL ;

# IO<9>
NET "BACKECHO" LOC = "P49" | IOSTANDARD = LVTTL ;