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cdf2018-principal/fpga/project.cfg

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PROJECT = Principal
TARGET_PART = xc3s200a-vq100
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
PROGRAMMER = mercpcl
TOPLEVEL = Principal
# Prod
# VHDSOURCE = $(TOPLEVEL).vhd uart.vhd
# CONSTRAINTS = mercury.ucf
# Debug
VHDSOURCE = $(TOPLEVEL).vhd $(filter-out %_tb.vhd,$(wildcard *.vhd))
CONSTRAINTS = debug.ucf
# Implement design
# Allow unmatched LOC Constraints
NGDBUILD_OPTS += -aul
# Allow unmatched Timing Group Constraints
NGDBUILD_OPTS += -aut