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https://github.com/RobotechLille/cdf2018-principal
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73 lines
2.2 KiB
VHDL
73 lines
2.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity sevenseg is
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Port (
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data : in STD_LOGIC_VECTOR (15 downto 0);
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clock : in STD_LOGIC;
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anode : out STD_LOGIC_VECTOR (3 downto 0);
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segment : out STD_LOGIC_VECTOR (6 downto 0);
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dot : out STD_LOGIC
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);
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end sevenseg;
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architecture structural of sevenseg is
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signal digit: std_logic_vector(3 downto 0);
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signal selector: integer := 0;
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signal counter : integer := 0;
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begin
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with selector select
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anode <= "1110" when 0,
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"1101" when 1,
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"1011" when 2,
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"0111" when 3,
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"0000" when others;
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with selector select
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digit <= data(3 downto 0) when 0,
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data(7 downto 4) when 1,
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data(11 downto 8) when 2,
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data(15 downto 12) when 3,
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"0000" when others;
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with digit select
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segment <= "0000001" when "0000", -- 0
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"1001111" when "0001", -- 1
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"0010010" when "0010", -- 2
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"0000110" when "0011", -- 3
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"1001100" when "0100", -- 4
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"0100100" when "0101", -- 5
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"0100000" when "0110", -- 6
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"0001111" when "0111", -- 7
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"0000000" when "1000", -- 8
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"0000100" when "1001", -- 9
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"0001000" when "1010", -- A
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"1100000" when "1011", -- b
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"0110001" when "1100", -- C
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"1000010" when "1101", -- d
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"0110000" when "1110", -- E
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"0111000" when "1111", -- F
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"0000000" when others;
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dot <= '1';
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alternateur : process(clock)
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begin
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if clock'event and clock = '1' then
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counter <= counter + 1;
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if counter >= 199999 then
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selector <= selector + 1;
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if selector >= 3 then
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selector <= 0;
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end if;
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counter <= 0;
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end if;
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end if;
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end process;
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end structural;
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