mirror of
https://github.com/RobotechLille/cdf2018-principal
synced 2024-11-23 16:46:04 +01:00
288 lines
9.8 KiB
VHDL
288 lines
9.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity Principal is
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Generic(
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fFpga : INTEGER := 50_000_000;
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fBaud : INTEGER := 115200
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);
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Port (
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CLK : in std_logic;
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BTN: in std_logic;
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RX: in std_logic;
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TX: out std_logic;
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LEFTCHA: in std_logic;
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LEFTCHB: in std_logic;
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RIGHTCHA: in std_logic;
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RIGHTCHB: in std_logic;
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FRONTTRIGGER: out std_logic;
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FRONTECHO: in std_logic;
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BACKTRIGGER: out std_logic;
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BACKECHO: in std_logic;
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ENAREF: out std_logic;
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ENA: out std_logic;
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IN1ENC: out std_logic;
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IN2: out std_logic;
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ENBREF: out std_logic;
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ENB: out std_logic;
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IN3END: out std_logic;
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IN4: out std_logic
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);
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end Principal;
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architecture Behavioral of Principal is
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-- General
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signal reset : std_logic := '0';
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-- Encoder
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signal left : integer;
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signal right : integer;
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signal zerocoder : std_logic;
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component hedm is
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Port (
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clk : in STD_LOGIC;
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chA : in STD_LOGIC;
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chB : in STD_LOGIC;
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reset : in STD_LOGIC;
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zero : in STD_LOGIC;
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counts : out integer
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);
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end component;
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-- Distance sensors
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signal front : integer := 0;
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signal frontRaw : integer := 0;
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signal frontFinished : std_logic;
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signal back : integer := 0;
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signal backRaw : integer := 0;
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signal backFinished : std_logic;
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component hcsr04 IS
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generic(
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fFpga : INTEGER := fFpga
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);
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port(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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echo : IN STD_LOGIC;
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distance : OUT INTEGER;
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trigger : OUT STD_LOGIC;
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start : IN STD_LOGIC;
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finished : OUT STD_LOGIC
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);
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end component;
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component fir is
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Port (
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clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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signalIn : in INTEGER;
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signalOut : out INTEGER;
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start : in STD_LOGIC;
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done : out STD_LOGIC
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);
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end component;
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-- PWM clock
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signal pwmClk : std_logic := '0';
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signal pwmCounter : integer := 0;
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constant PWM_DIVIDER : integer := 4096;
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-- Motor controller
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signal enAd : std_logic_vector(7 downto 0);
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signal in1enCd : std_logic_vector(7 downto 0);
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signal in2d : std_logic;
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signal enBd : std_logic_vector(7 downto 0);
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signal in3enDd : std_logic_vector(7 downto 0);
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signal in4d : std_logic;
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component PWM is
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port (
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clk : in std_logic;
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data : in std_logic_vector (7 downto 0);
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pulse : out std_logic
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);
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end component;
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-- CF
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component uart is
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generic (
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baud : positive := fBaud;
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clock_frequency : positive := fFpga
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);
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port (
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clock : in std_logic;
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reset : in std_logic;
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data_stream_in : in std_logic_vector(7 downto 0);
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data_stream_in_stb : in std_logic;
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data_stream_in_ack : out std_logic;
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data_stream_out : out std_logic_vector(7 downto 0);
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data_stream_out_stb : out std_logic;
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tx : out std_logic;
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rx : in std_logic
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);
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end component;
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signal txData : std_logic_vector(7 downto 0);
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signal txStb : std_logic := '0';
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signal txAck : std_logic := '0';
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signal rxData : std_logic_vector(7 downto 0);
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signal rxStb : std_logic := '0';
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-- Handling
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component communication is
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Port (
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clock : in std_logic;
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reset : in std_logic;
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left : in integer;
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right : in integer;
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zerocoder : out std_logic;
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front : in integer;
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back : in integer;
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txData : out std_logic_vector(7 downto 0);
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txStb : out std_logic;
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txAck : in std_logic;
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rxData : in std_logic_vector(7 downto 0);
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rxStb : in std_logic;
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enA : out std_logic_vector(7 downto 0);
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in1enC : out std_logic_vector(7 downto 0);
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in2 : out std_logic;
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enB : out std_logic_vector(7 downto 0);
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in3enD : out std_logic_vector(7 downto 0);
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in4 : out std_logic
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);
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end component;
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begin
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reset <= BTN;
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pwmClkGenerator: process (clk) begin
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if rising_edge(clk) then
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if (pwmCounter >= PWM_DIVIDER) then
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pwmClk <= not pwmClk;
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pwmCounter <= 0;
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else
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pwmCounter <= pwmCounter + 1;
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end if;
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end if;
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end process;
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leftCoder: hedm port map (
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clk => CLK,
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chA => LEFTCHA,
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chB => LEFTCHB,
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reset => reset,
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zero => zerocoder,
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counts => left
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);
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rightCoder: hedm port map (
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clk => CLK,
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chA => RIGHTCHA,
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chB => RIGHTCHB,
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reset => reset,
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zero => zerocoder,
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counts => right
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);
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frontCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => FRONTECHO,
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distance => frontRaw,
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trigger => FRONTTRIGGER,
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start => '1',
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finished => frontFinished
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);
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frontFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => frontRaw,
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signalOut => front,
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start => frontFinished
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-- done => done
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);
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backCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => BACKECHO,
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distance => backRaw,
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trigger => BACKTRIGGER,
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start => '1',
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finished => backFinished
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);
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backFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => backRaw,
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signalOut => back,
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start => backFinished
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-- done => done
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);
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enAp : PWM port map (
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clk => pwmClk,
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data => enAd,
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pulse => ENA
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);
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ENAREF <= '1';
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in1enCp : PWM port map (
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clk => pwmClk,
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data => in1enCd,
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pulse => IN1ENC
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);
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IN2 <= in2d;
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enBp : PWM port map (
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clk => pwmClk,
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data => enBd,
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pulse => ENB
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);
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ENBREF <= '1';
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in3enDp : PWM port map (
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clk => pwmClk,
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data => in3enDd,
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pulse => IN3END
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);
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IN4 <= in4d;
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FA: uart port map(
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clock => CLK,
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reset => reset,
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data_stream_in => txData,
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data_stream_in_stb => txStb,
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data_stream_in_ack => txAck,
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data_stream_out => rxData,
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data_stream_out_stb => rxStb,
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tx => TX,
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rx => RX
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);
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com: communication port map(
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clock => CLK,
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reset => reset,
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left => left,
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right => right,
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zerocoder => zerocoder,
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front => front,
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back => back,
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txData => txData,
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txStb => txStb,
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txAck => txAck,
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rxData => rxData,
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rxStb => rxStb,
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enA => enAd,
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in1enC => in1enCd,
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in2 => in2d,
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enB => enBd,
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in3enD => in3enDd,
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in4 => in4d
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);
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end Behavioral;
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