mirror of
https://github.com/RobotechLille/cdf2018-principal
synced 2024-11-21 15:46:06 +01:00
284 lines
6.8 KiB
VHDL
284 lines
6.8 KiB
VHDL
--###############################
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--# Project Name : I2C slave
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--# File : i2cslave.vhd
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--# Project : i2c slave for FPGA
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--# Engineer : Philippe THIRION
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--# Modification History
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--###############################
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-- copyright Philippe Thirion
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-- github.com/tirfil
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--
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-- Copyright 2016 Philippe THIRION
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity I2CSLAVE is
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generic(
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DEVICE : std_logic_vector(7 downto 0) := x"38"
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);
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port(
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MCLK : in std_logic;
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nRST : in std_logic;
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SDA_IN : in std_logic;
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SCL_IN : in std_logic;
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SDA_OUT : out std_logic;
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SCL_OUT : out std_logic;
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ADDRESS : out std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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DATA_IN : in std_logic_vector(7 downto 0);
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WR : out std_logic;
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RD : out std_logic
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);
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end I2CSLAVE;
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architecture rtl of I2CSLAVE is
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type tstate is ( S_IDLE, S_START, S_SHIFTIN, S_RW, S_SENDACK, S_SENDACK2, S_SENDNACK,
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S_ADDRESS, S_WRITE, S_SHIFTOUT, S_READ, S_WAITACK
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);
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type toperation is (OP_READ, OP_WRITE);
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signal state : tstate;
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signal next_state : tstate;
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signal operation : toperation;
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signal rising_scl, falling_scl : std_logic;
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signal address_i : std_logic_vector(7 downto 0);
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signal next_address : std_logic_vector(7 downto 0);
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signal counter : integer range 0 to 7;
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signal start_cond : std_logic;
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signal stop_cond : std_logic;
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signal sda_q, sda_qq, sda_qqq : std_logic;
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signal scl_q, scl_qq, scl_qqq : std_logic;
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signal shiftreg : std_logic_vector(7 downto 0);
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signal sda: std_logic;
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signal address_incr : std_logic;
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signal rd_d : std_logic;
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begin
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ADDRESS <= address_i;
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next_address <= (others=>'0') when (address_i = x"FF") else
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std_logic_vector(to_unsigned(to_integer(unsigned( address_i )) + 1, 8));
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S_RSY: process(MCLK,nRST)
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begin
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if (nRST = '0') then
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sda_q <= '1';
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sda_qq <= '1';
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sda_qqq <= '1';
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scl_q <= '1';
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scl_qq <= '1';
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scl_qqq <= '1';
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elsif (MCLK'event and MCLK='1') then
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sda_q <= SDA_IN;
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sda_qq <= sda_q;
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sda_qqq <= sda_qq;
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scl_q <= SCL_IN;
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scl_qq <= scl_q;
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scl_qqq <= scl_qq;
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end if;
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end process S_RSY;
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rising_scl <= scl_qq and not scl_qqq;
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falling_scl <= not scl_qq and scl_qqq;
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START_BIT: process(MCLK,nRST)
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begin
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if (nRST = '0') then
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start_cond <= '0';
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elsif (MCLK'event and MCLK='1') then
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if (sda_qqq = '1' and sda_qq = '0' and scl_qq = '1') then
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start_cond <= '1';
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else
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start_cond <= '0';
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end if;
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end if;
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end process START_BIT;
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STOP_BIT: process(MCLK,nRST)
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begin
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if (nRST = '0') then
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stop_cond <= '0';
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elsif (MCLK'event and MCLK='1') then
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if (sda_qqq = '0' and sda_qq = '1' and scl_qq = '1') then
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stop_cond <= '1';
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else
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stop_cond <= '0';
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end if;
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end if;
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end process STOP_BIT;
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sda <= sda_qq;
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RD_DELAY: process(MCLK, nRST)
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begin
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if (nRST = '0') then
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RD <= '0';
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elsif (MCLK'event and MCLK='1') then
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RD <= rd_d;
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end if;
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end process RD_DELAY;
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OTO: process(MCLK, nRST)
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begin
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if (nRST = '0') then
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state <= S_IDLE;
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SDA_OUT <= '1';
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SCL_OUT <= '1';
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WR <= '0';
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rd_d <= '0';
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address_i <= (others=>'0');
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DATA_OUT <= (others=>'0');
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shiftreg <= (others=>'0');
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elsif (MCLK'event and MCLK='1') then
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if (stop_cond = '1') then
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state <= S_IDLE;
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SDA_OUT <= '1';
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SCL_OUT <= '1';
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operation <= OP_READ;
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WR <= '0';
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rd_d <= '0';
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address_incr <= '0';
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elsif(start_cond = '1') then
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state <= S_START;
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SDA_OUT <= '1';
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SCL_OUT <= '1';
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operation <= OP_READ;
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WR <= '0';
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rd_d <= '0';
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address_incr <= '0';
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elsif(state = S_IDLE) then
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state <= S_IDLE;
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SDA_OUT <= '1';
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SCL_OUT <= '1';
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operation <= OP_READ;
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WR <= '0';
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rd_d <= '0';
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address_incr <= '0';
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elsif(state = S_START) then
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shiftreg <= (others=>'0');
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state <= S_SHIFTIN;
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next_state <= S_RW;
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counter <= 6;
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elsif(state = S_SHIFTIN) then
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if (rising_scl = '1') then
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shiftreg(7 downto 1) <= shiftreg(6 downto 0);
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shiftreg(0) <= sda;
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if (counter = 0) then
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state <= next_state;
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counter <= 7;
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else
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counter <= counter - 1;
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end if;
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end if;
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elsif(state = S_RW) then
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if (rising_scl = '1') then
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if (shiftreg = DEVICE) then
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state <= S_SENDACK;
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if (sda = '1') then
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operation <= OP_READ;
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-- next_state <= S_READ; -- no needed
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rd_d <= '1';
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else
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operation <= OP_WRITE;
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next_state <= S_ADDRESS;
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address_incr <= '0';
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end if;
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else
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state <= S_SENDNACK;
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end if;
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end if;
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elsif(state = S_SENDACK) then
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WR <= '0';
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rd_d <= '0';
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if (falling_scl = '1') then
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SDA_OUT <= '0';
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counter <= 7;
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if (operation= OP_WRITE) then
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state <= S_SENDACK2;
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else -- OP_READ
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state <= S_SHIFTOUT;
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shiftreg <= DATA_IN;
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end if;
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end if;
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elsif(state = S_SENDACK2) then
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if (falling_scl = '1') then
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SDA_OUT <= '1';
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state <= S_SHIFTIN;
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shiftreg <= (others=>'0');
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if (address_incr = '1') then
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address_i <= next_address;
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end if;
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end if;
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elsif(state = S_SENDNACK) then
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if (falling_scl = '1') then
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SDA_OUT <= '1';
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state <= S_IDLE;
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end if;
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elsif(state = S_ADDRESS) then
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address_i <= shiftreg;
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next_state <= S_WRITE;
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state <= S_SENDACK;
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address_incr <= '0';
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elsif(state = S_WRITE) then
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DATA_OUT <= shiftreg;
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next_state <= S_WRITE;
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state <= S_SENDACK;
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WR <= '1';
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address_incr <= '1';
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elsif(state = S_SHIFTOUT) then
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if (falling_scl = '1') then
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SDA_OUT <= shiftreg(7);
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shiftreg(7 downto 1) <= shiftreg(6 downto 0);
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shiftreg(0) <= '1';
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if (counter = 0) then
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state <= S_READ;
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address_i <= next_address;
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rd_d <= '1';
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else
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counter <= counter - 1;
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end if;
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end if;
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elsif(state = S_READ) then
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rd_d <= '0';
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if (falling_scl = '1') then
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SDA_OUT <= '1';
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state <= S_WAITACK;
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end if;
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elsif(state = S_WAITACK) then
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if (rising_scl = '1') then
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if (sda = '0') then
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state <= S_SHIFTOUT;
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counter <= 7;
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shiftreg <= DATA_IN;
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else
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state <= S_IDLE;
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end if;
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end if;
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end if;
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end if;
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end process OTO;
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end rtl;
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