.equ PINA = 0x00 ; définition des adresses des ports .equ DDRA = 0x01 .equ PORTA = 0x02 .equ PINB = 0x03 .equ DDRB = 0x04 .equ PORTB = 0x05 .equ RAMEND = 0x21FF .equ SPH = 0x3E ; initialisation de la pile .equ SPL = 0x3D .equ SREG = 0x3F .equ ADMUX = 0x7C .equ ADCSRB = 0x7B .equ ADCSRA = 0x7A .equ ADCH = 0x79 .equ ADCL = 0x78 .def temp = r20 .def consigne = r21 .org 0x000 ; Vecteur RESET jmp debut .org 0x0080 codeAff: .db 0b1111110, 0b001100 .db 0b0110111, 0b0011111 .db 0b1001101, 0b1011011 .db 0b1111011, 0b0001110 .db 0b1111111, 0b1011111 debut: ldi r28, low(RAMEND) ldi r29, high(RAMEND) out SPL, r28 out SPH, r29 ; DDRA@IO <- 0b01111111 LDI R16,0b01111111 OUT DDRA,R16 ; DDRB@IO <- 0xFF LDI R16,0xFF OUT DDRB,R16 ; ADCSRB <- 0b00000000 LDI R16,0b00000000 STS ADCSRB,R16 boucle: ; ADMUX <- 0b01100000 LDI R16,0b01100000 STS ADMUX,R16 ; ADCSRA <- 0b11100111 LDI R16,0b11100111 STS ADCSRA,R16 ;ADCSRB <- 0b01000010 attente1: ; si (ADCSRA & 0b00010000) = 0 saut attente1 LDS R16,ADCSRA ANDI R16,0b00010000 PUSH R16 LDI R16,0 POP R17 CP R17,R16 BREQ eti0 CLR R16 RJMP eti1 eti0: LDI R16,0x01 eti1: TST R16 BREQ eti2 JMP attente1 eti2: ; r5 <- ADCH LDS R16,ADCH MOV R5,R16 ;ADCSRA <- ADCSRA & 0b11101111 ;consigne <- ADCH / 8 + 20 ;si (PORTA@IO & 0b10000000) = 0 alors consigne <- 12 ; ADMUX <- 0b01100001 LDI R16,0b01100001 STS ADMUX,R16 ; ADCSRA <- 0b11100111 LDI R16,0b11100111 STS ADCSRA,R16 ;ADCSRB <- 0b01000010 attente2: ; si (ADCSRA & 0b00010000) = 0 saut attente2 LDS R16,ADCSRA ANDI R16,0b00010000 PUSH R16 LDI R16,0 POP R17 CP R17,R16 BREQ eti3 CLR R16 RJMP eti4 eti3: LDI R16,0x01 eti4: TST R16 BREQ eti5 JMP attente2 eti5: ; r6 <- ADCH LDS R16,ADCH MOV R6,R16 ;ADCSRA <- ADCSRA & 0b11101111 ;temp <- ADCH / 4 ;PORTA@IO <- codeAff@ROM[temp/20] ;PORTB@IO <- codeAff@ROM[temp-(temp/20)*20] ;si consigne - 1 > temp alors PORTB@IO <- PORTB@IO | 0b10000000 ;si consigne + 1 < temp alors PORTB@IO <- PORTB@IO & 0b01111111 ;PORTB@IO <- PORTB@IO | 0b10000000 jmp boucle