385 lines
6.2 KiB
NASM
385 lines
6.2 KiB
NASM
.equ PINA = 0x00 ; définition des adresses des ports
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.equ DDRA = 0x01
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.equ PORTA = 0x02
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.equ PINB = 0x03
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.equ DDRB = 0x04
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.equ PORTB = 0x05
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.equ EIMSK = 0x3D
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.equ EICRA = 0x69
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.equ EICRB = 0x6A
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.equ SREG = 0x3F
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.equ WDTCSR = 0x60
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.equ RAMEND = 0x21FF
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.equ SPH = 0x3E ; initialisation de la pile
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.equ SPL = 0x3D
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.def chen = r19
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.def port = r20
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.org 0x000
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; Vecteur RESET
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jmp debut
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.org 0x0002 ; Définition du code à éxecuter lors des interruption
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jmp horaire
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.org 0x0004 ; Définition du code à éxecuter lors des interruption
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jmp antihoraire
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.org 0x0080
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debut:
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; DDRA@IO <- 0xFF ; Configuration des ports A et B en sortie
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LDI R16,0xFF
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OUT DDRA,R16
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; DDRB@IO <- 0xFF
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LDI R16,0xFF
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OUT DDRB,R16
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; EIMSK <- 0b00000011 ; On active les interruptions PD0 et PD1 sur front descendant
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LDI R16,0b00000011
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STS EIMSK,R16
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; EICRA <- 0b00001010
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LDI R16,0b00001010
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STS EICRA,R16
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; EICRB <- 0b00000000
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LDI R16,0b00000000
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STS EICRB,R16
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; On active les interruptions au niveau du µP
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; SREG <- 0b10000000
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LDI R16,0b10000000
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STS SREG,R16
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; chen <- 0b00000001
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LDI R16,0b00000001
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STS chen,R16
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; chen <- 0xAA
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LDI R16,0xAA
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STS chen,R16
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; port <- 0x00 ; pair : port A, impair : port B
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LDI R16,0x00
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STS port,R16
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call afficher
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sei
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boucle:
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sleep ; On ne fait rien jusqu'à la prochaine interruption
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; jump boucle
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JMP boucle
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horaire:
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; si (port & 0x01) == 0 alors lsl chen
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; si (port & 0x01) == 0 alors chen <- chen * 2
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti0
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CLR R16
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RJMP eti1
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eti0:
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LDI R16,0x01
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eti1:
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TST R16
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BREQ eti2
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LDS R16,chen
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LDI R17,2
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MUL R16,R17
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MOV R16,R0
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STS chen,R16
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eti2:
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; si (port & 0x01) == 1 alors lsr chen
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; si (port & 0x01) == 1 alors chen <- chen / 2
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,1
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POP R17
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CP R17,R16
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BREQ eti3
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CLR R16
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RJMP eti4
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eti3:
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LDI R16,0x01
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eti4:
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TST R16
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BREQ eti6
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LDS R16,chen
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LDI R17,2
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SER R18
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eti5:
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INC R18
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SUB R16,R17
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BRCC eti5
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MOV R16,R18
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STS chen,R16
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eti6:
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; si chen != 0 saut finhoraire
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LDS R16,chen
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BRNE eti7
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CLR R16
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RJMP eti8
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eti7:
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LDI R16,0x01
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eti8:
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TST R16
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BREQ eti9
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JMP finhoraire
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eti9:
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; si (port & 0x01) == 0 alors chen <- 0b10000000
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti10
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CLR R16
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RJMP eti11
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eti10:
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LDI R16,0x01
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eti11:
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TST R16
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BREQ eti12
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LDI R16,0b10000000
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STS chen,R16
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eti12:
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; si (port & 0x01) == 1 alors chen <- 0b00000001
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,1
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POP R17
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CP R17,R16
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BREQ eti13
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CLR R16
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RJMP eti14
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eti13:
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LDI R16,0x01
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eti14:
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TST R16
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BREQ eti15
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LDI R16,0b00000001
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STS chen,R16
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eti15:
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inc port
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finhoraire:
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call afficher
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reti
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antihoraire:
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; si (port & 0x01) == 0 alors lsr chen
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; si (port & 0x01) == 0 alors chen <- chen / 2
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti16
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CLR R16
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RJMP eti17
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eti16:
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LDI R16,0x01
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eti17:
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TST R16
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BREQ eti19
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LDS R16,chen
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LDI R17,2
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SER R18
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eti18:
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INC R18
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SUB R16,R17
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BRCC eti18
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MOV R16,R18
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STS chen,R16
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eti19:
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; si (port & 0x01) == 1 alors lsl chen
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; si (port & 0x01) == 1 alors chen <- chen * 2
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,1
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POP R17
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CP R17,R16
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BREQ eti20
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CLR R16
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RJMP eti21
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eti20:
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LDI R16,0x01
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eti21:
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TST R16
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BREQ eti22
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LDS R16,chen
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LDI R17,2
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MUL R16,R17
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MOV R16,R0
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STS chen,R16
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eti22:
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; si chen != 0 saut finantihoraire
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LDS R16,chen
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BRNE eti23
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CLR R16
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RJMP eti24
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eti23:
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LDI R16,0x01
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eti24:
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TST R16
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BREQ eti25
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JMP finantihoraire
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eti25:
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; si (port & 0x01) == 0 alors chen <- 0b00000001
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti26
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CLR R16
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RJMP eti27
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eti26:
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LDI R16,0x01
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eti27:
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TST R16
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BREQ eti28
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LDI R16,0b00000001
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STS chen,R16
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eti28:
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; si (port & 0x01) == 1 alors chen <- 0b10000000
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,1
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POP R17
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CP R17,R16
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BREQ eti29
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CLR R16
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RJMP eti30
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eti29:
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LDI R16,0x01
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eti30:
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TST R16
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BREQ eti31
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LDI R16,0b10000000
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STS chen,R16
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eti31:
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inc port
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finantihoraire:
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call afficher
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reti
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afficher:
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; si (port & 0x01) == 0 alors PORTB@IO <- 0x00
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti32
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CLR R16
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RJMP eti33
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eti32:
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LDI R16,0x01
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eti33:
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TST R16
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BREQ eti34
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LDI R16,0x00
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OUT PORTB,R16
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eti34:
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; si (port & 0x01) == 1 alors PORTA@IO <- 0x00
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,1
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POP R17
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CP R17,R16
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BREQ eti35
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CLR R16
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RJMP eti36
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eti35:
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LDI R16,0x01
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eti36:
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TST R16
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BREQ eti37
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LDI R16,0x00
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OUT PORTA,R16
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eti37:
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; si (port & 0x01) == 0 alors PORTA@IO <- chen
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti38
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CLR R16
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RJMP eti39
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eti38:
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LDI R16,0x01
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eti39:
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TST R16
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BREQ eti40
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LDS R16,chen
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OUT PORTA,R16
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eti40:
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; si (port & 0x01) == 1 alors PORTB@IO <- chen
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LDS R16,port
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ANDI R16,0x01
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PUSH R16
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LDI R16,1
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POP R17
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CP R17,R16
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BREQ eti41
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CLR R16
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RJMP eti42
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eti41:
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LDI R16,0x01
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eti42:
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TST R16
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BREQ eti43
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LDS R16,chen
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OUT PORTB,R16
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eti43:
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ret
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