213 lines
3.3 KiB
NASM
213 lines
3.3 KiB
NASM
.equ PINA = 0x00 ; définition des adresses des ports
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.equ DDRA = 0x01
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.equ PORTA = 0x02
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.equ PINB = 0x03
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.equ DDRB = 0x04
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.equ PORTB = 0x05
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.equ PINC = 0x06
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.equ DDRC = 0x07
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.equ PORTC = 0x08
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.equ SREG = 0x3F
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.equ WDTCSR = 0x60
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.equ TCCR0A = 0x24
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.equ TCCR0B = 0x25
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.equ TIMSK0 = 0x6E
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.equ TIFR0 = 0x35
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.equ RAMEND = 0x21FF
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.equ SPH = 0x3E ; initialisation de la pile
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.equ SPL = 0x3D
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.def d2 = r19
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.def d1 = r20
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.def d0 = r21
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.def select = r22
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.org 0x000
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; Vecteur RESET
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jmp debut
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.org 0x0018
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jmp wd
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.org 0x002E
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jmp tm
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.org 0x0080
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afficheur:
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.DB 0x7E, 0x0C, 0x37, 0x9F, 0x4D, 0xDB, 0xFB, 0x0E, 0xFF, 0xDF
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; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
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debut:
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; d2 <- 0
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LDI R16,0
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STS d2,R16
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; d1 <- 0
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LDI R16,0
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STS d1,R16
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; d0 <- 0
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LDI R16,0
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STS d0,R16
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; select <- 0x01
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LDI R16,0x01
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STS select,R16
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cli
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; SREG <- 0b10000000
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LDI R16,0b10000000
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STS SREG,R16
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; Configuration des ports
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; DDRA@IO <- 0xFF
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LDI R16,0xFF
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OUT DDRA,R16
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; DDRB@IO <- 0xFF
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LDI R16,0xFF
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OUT DDRB,R16
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; DDRC@IO <- 0xFF
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LDI R16,0xFF
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OUT DDRC,R16
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; Watchdog toutes les secondes
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; WDTCSR <- 0x10
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LDI R16,0x10
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STS WDTCSR,R16
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; WDTCSR <- 0b01000110
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LDI R16,0b01000110
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STS WDTCSR,R16
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; Timer toutes les 8-16ms
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;TCCR0A@IO <- 0x00
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;TCCR0B@IO <- 0x04
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;TIMSK0 <- 0x01
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;TIFR0 <- 0x01
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sei
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boucle:
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sleep
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; jump boucle
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JMP boucle
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wd:
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inc d0
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; si d0 < 10 saut finwd
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LDS R16,d0
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti0
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CLR R16
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RJMP eti1
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eti0:
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LDI R16,0x01
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eti1:
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TST R16
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BREQ eti2
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JMP finwd
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eti2:
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; d0 <- 0
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LDI R16,0
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STS d0,R16
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inc d1
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; si d1 < 10 saut finwd
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LDS R16,d1
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti3
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CLR R16
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RJMP eti4
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eti3:
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LDI R16,0x01
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eti4:
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TST R16
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BREQ eti5
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JMP finwd
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eti5:
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; d1 <- 0
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LDI R16,0
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STS d1,R16
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inc d2
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; si d2 < 10 saut finwd
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LDS R16,d2
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti6
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CLR R16
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RJMP eti7
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eti6:
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LDI R16,0x01
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eti7:
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TST R16
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BREQ eti8
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JMP finwd
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eti8:
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; d2 <- 0
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LDI R16,0
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STS d2,R16
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finwd:
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; PORTA@IO <- afficheur@ROM[d1]
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LDS R16,d1
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LDI R30,low(afficheur<<1)
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LDI R31,high(afficheur<<1)
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CLR R17
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ADD R30,R16
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ADC R31,R17
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LPM R16,Z
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OUT PORTA,R16
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; PORTC@IO <- 0x40
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LDI R16,0x40
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OUT PORTC,R16
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reti
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tm:
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;PortC@IO <- select
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;si select = 0x80 alors PortA@IO <- afficheur@ROM[d0]
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;si select = 0x40 alors PortA@IO <- afficheur@ROM[d1]
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;si select = 0x20 alors PortA@IO <- afficheur@ROM[d2]
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;lsl select
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;si select = 0 alors select <- 0x20
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;PORTC@IO <- afficheur@ROM[d0]
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;PORTB@IO <- afficheur@ROM[d1]
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; PORTA@IO <- afficheur@ROM[d2]
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LDS R16,d2
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LDI R30,low(afficheur<<1)
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LDI R31,high(afficheur<<1)
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CLR R17
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ADD R30,R16
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ADC R31,R17
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LPM R16,Z
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OUT PORTA,R16
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; PORTC@IO <- 0x40
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LDI R16,0x40
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OUT PORTC,R16
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reti
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