313 lines
4.3 KiB
NASM
313 lines
4.3 KiB
NASM
.equ PINA = 0x00 ; définition des adresses des ports
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.equ DDRA = 0x01
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.equ PORTA = 0x02
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.equ PINB = 0x03
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.equ DDRB = 0x04
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.equ PORTB = 0x05
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.equ PIND = 0x09
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.equ DDRD = 0x0A
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.equ PORTD = 0x0B
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.equ SREG = 0x3F
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.equ WDTCSR = 0x60
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.equ TCCR0A = 0x24
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.equ TCCR0B = 0x25
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.equ TIMSK0 = 0x6E
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.equ TIFR0 = 0x35
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.equ EIMSK = 0x3D
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.equ EICRA = 0x69
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.equ EICRB = 0x6A
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.equ RAMEND = 0x21FF
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.equ SPH = 0x3E ; initialisation de la pile
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.equ SPL = 0x3D
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.def d1 = r20
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.def d0 = r21
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.def route = r22
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.org 0x000
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; Vecteur RESET
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jmp debut
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.org 0x0002
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jmp b10s
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.org 0x0004
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jmp b1s
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.org 0x0006
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jmp marche
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.org 0x0008
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jmp arret
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.org 0x0018
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jmp wd
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.org 0x0080
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afficheur:
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.DB 0x7E, 0x0C, 0x37, 0x9F, 0x4D, 0xDB, 0xFB, 0x0E, 0xFF, 0xDF
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; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
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debut:
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; d1 <- 0
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LDI R16,0
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STS d1,R16
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; d0 <- 0
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LDI R16,0
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STS d0,R16
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; route <- 0
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LDI R16,0
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STS route,R16
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cli
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; SREG <- 0b10000000
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LDI R16,0b10000000
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STS SREG,R16
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; Configuration des ports
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; DDRA@IO <- 0xFF
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LDI R16,0xFF
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OUT DDRA,R16
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; DDRB@IO <- 0xFF
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LDI R16,0xFF
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OUT DDRB,R16
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; DDRD@IO <- 0x80
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LDI R16,0x80
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OUT DDRD,R16
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; Interruptions
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; EIMSK <- 0b00001111 ; On active les interruptions PD[3:0] sur front descendant
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LDI R16,0b00001111
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STS EIMSK,R16
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; EICRA <- 0b10101010
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LDI R16,0b10101010
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STS EICRA,R16
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; EICRB <- 0b00000000
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LDI R16,0b00000000
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STS EICRB,R16
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; Watchdog toutes les secondes
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; WDTCSR <- 0x10
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LDI R16,0x10
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STS WDTCSR,R16
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; WDTCSR <- 0b01000110
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LDI R16,0b01000110
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STS WDTCSR,R16
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sei
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call affiche
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boucle:
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sleep
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; jump boucle
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JMP boucle
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b1s:
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inc d0
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; si d0 < 10 saut finb1s
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LDS R16,d0
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti0
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CLR R16
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RJMP eti1
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eti0:
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LDI R16,0x01
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eti1:
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TST R16
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BREQ eti2
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JMP finb1s
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eti2:
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; d0 <- 0
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LDI R16,0
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STS d0,R16
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; jump b10s
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JMP b10s
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finb1s:
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call affiche
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reti
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b10s:
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inc d1
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; si d1 < 10 saut finb10s
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LDS R16,d1
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti3
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CLR R16
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RJMP eti4
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eti3:
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LDI R16,0x01
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eti4:
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TST R16
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BREQ eti5
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JMP finb10s
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eti5:
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; d0 <- 9
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LDI R16,9
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STS d0,R16
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; d1 <- 9
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LDI R16,9
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STS d1,R16
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finb10s:
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call affiche
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reti
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affiche:
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; PORTA@IO <- afficheur@ROM[d1]
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LDS R16,d1
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LDI R30,low(afficheur<<1)
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LDI R31,high(afficheur<<1)
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CLR R17
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ADD R30,R16
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ADC R31,R17
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LPM R16,Z
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OUT PORTA,R16
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; PORTB@IO <- afficheur@ROM[d0]
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LDS R16,d0
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LDI R30,low(afficheur<<1)
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LDI R31,high(afficheur<<1)
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CLR R17
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ADD R30,R16
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ADC R31,R17
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LPM R16,Z
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OUT PORTB,R16
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ret
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marche:
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; route <- 1
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LDI R16,1
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STS route,R16
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; PORTD@IO <- 0x80
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LDI R16,0x80
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OUT PORTD,R16
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reti
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arret:
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; route <- 0
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LDI R16,0
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STS route,R16
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; d0 <- 0
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LDI R16,0
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STS d0,R16
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; d1 <- 0
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LDI R16,0
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STS d1,R16
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call affiche
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reti
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wd:
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; si route = 0 saut finwd
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LDS R16,route
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PUSH R16
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LDI R16,0
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POP R17
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CP R17,R16
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BREQ eti6
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CLR R16
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RJMP eti7
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eti6:
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LDI R16,0x01
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eti7:
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TST R16
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BREQ eti8
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JMP finwd
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eti8:
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dec d0
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; si d0 < 10 saut prefinwd
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LDS R16,d0
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti9
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CLR R16
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RJMP eti10
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eti9:
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LDI R16,0x01
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eti10:
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TST R16
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BREQ eti11
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JMP prefinwd
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eti11:
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; d0 <- 9
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LDI R16,9
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STS d0,R16
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dec d1
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; si d1 < 10 saut prefinwd
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LDS R16,d1
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PUSH R16
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LDI R16,10
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POP R17
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CP R17,R16
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BRLO eti12
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CLR R16
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RJMP eti13
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eti12:
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LDI R16,0x01
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eti13:
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TST R16
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BREQ eti14
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JMP prefinwd
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eti14:
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; route <- 0
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LDI R16,0
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STS route,R16
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; PORTD@IO <- 0x00
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LDI R16,0x00
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OUT PORTD,R16
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; d0 <- 0
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LDI R16,0
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STS d0,R16
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; d1 <- 0
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LDI R16,0
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STS d1,R16
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prefinwd:
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call affiche
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finwd:
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reti
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