geoffrey/cdf2018-principal
geoffrey/cdf2018-principal
1
0
Fork 0
mirror of https://github.com/RobotechLille/cdf2018-principal synced 2024-11-14 04:16:05 +01:00
Code Issues Releases Wiki Activity

FPGA : Suppression délai inutile encodeurs

Browse source
This commit is contained in:
Geoffrey Frogeye 2018-03-02 15:01:48 +01:00
parent 6082662c2d
commit 5c1ccbce93
2 changed files with 12 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
fpga/hedm.vhd
View file

@ -20,7 +20,6 @@ entity hedm is
end hedm;
architecture Behavioral of hedm is
signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
begin
processInput : process(clk, reset)
@ -29,18 +28,10 @@ begin
if reset = '1' then
counter := 0;
counts <= 0;
An <= '0';
Bn <= '0';
Ap <= '0';
Bp <= '0';
elsif rising_edge(clk) then
Ap <= An;
Bp <= Bn;
An <= chA;
Bn <= chB;
if zero = '1' then
counter := 0;
end if;
@ -49,32 +40,35 @@ begin
-- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
-- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
if (Ap = '0' and An = '1') then -- Front montant A
if (Bn = '0') then
if (Ap = '0' and chA = '1') then -- Front montant A
if (chB = '0') then
counter := counter + 1;
else
counter := counter - 1;
end if;
elsif (Ap = '1' and An = '0') then -- Front descendant A
if (Bn = '1') then
elsif (Ap = '1' and chA = '0') then -- Front descendant A
if (chB = '1') then
counter := counter + 1;
else
counter := counter - 1;
end if;
elsif (Bp = '0' and Bn = '1') then -- Front montant B
if (An = '1') then
elsif (Bp = '0' and chB = '1') then -- Front montant B
if (chA = '1') then
counter := counter + 1;
else
counter := counter - 1;
end if;
elsif (Bp = '1' and Bn = '0') then -- Front descendant B
if (An = '0') then
elsif (Bp = '1' and chB = '0') then -- Front descendant B
if (chA = '0') then
counter := counter + 1;
else
counter := counter - 1;
end if;
end if;
Ap <= chA;
Bp <= chB;
counts <= counter;
end if;

2
fpga/hedm_tb.vhd
View file

@ -112,7 +112,7 @@ begin
wait for TbPeriod;
wait for 5 * TbPeriod;
assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
assert counts = 2 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
zero <= '1';
wait for TbPeriod;