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FPGA : Suppression délai inutile encodeurs
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@ -20,7 +20,6 @@ entity hedm is
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end hedm;
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end hedm;
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architecture Behavioral of hedm is
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architecture Behavioral of hedm is
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signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
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signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
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signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
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begin
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begin
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processInput : process(clk, reset)
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processInput : process(clk, reset)
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@ -29,18 +28,10 @@ begin
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if reset = '1' then
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if reset = '1' then
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counter := 0;
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counter := 0;
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counts <= 0;
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counts <= 0;
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An <= '0';
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Bn <= '0';
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Ap <= '0';
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Ap <= '0';
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Bp <= '0';
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Bp <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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Ap <= An;
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Bp <= Bn;
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An <= chA;
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Bn <= chB;
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if zero = '1' then
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if zero = '1' then
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counter := 0;
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counter := 0;
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end if;
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end if;
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@ -49,32 +40,35 @@ begin
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-- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
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-- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
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-- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
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-- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
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if (Ap = '0' and An = '1') then -- Front montant A
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if (Ap = '0' and chA = '1') then -- Front montant A
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if (Bn = '0') then
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if (chB = '0') then
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counter := counter + 1;
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counter := counter + 1;
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else
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else
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counter := counter - 1;
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counter := counter - 1;
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end if;
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end if;
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elsif (Ap = '1' and An = '0') then -- Front descendant A
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elsif (Ap = '1' and chA = '0') then -- Front descendant A
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if (Bn = '1') then
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if (chB = '1') then
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counter := counter + 1;
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counter := counter + 1;
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else
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else
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counter := counter - 1;
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counter := counter - 1;
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end if;
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end if;
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elsif (Bp = '0' and Bn = '1') then -- Front montant B
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elsif (Bp = '0' and chB = '1') then -- Front montant B
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if (An = '1') then
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if (chA = '1') then
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counter := counter + 1;
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counter := counter + 1;
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else
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else
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counter := counter - 1;
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counter := counter - 1;
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end if;
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end if;
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elsif (Bp = '1' and Bn = '0') then -- Front descendant B
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elsif (Bp = '1' and chB = '0') then -- Front descendant B
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if (An = '0') then
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if (chA = '0') then
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counter := counter + 1;
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counter := counter + 1;
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else
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else
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counter := counter - 1;
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counter := counter - 1;
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end if;
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end if;
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end if;
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end if;
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Ap <= chA;
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Bp <= chB;
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counts <= counter;
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counts <= counter;
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end if;
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end if;
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@ -112,7 +112,7 @@ begin
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wait for TbPeriod;
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wait for TbPeriod;
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wait for 5 * TbPeriod;
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wait for 5 * TbPeriod;
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assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
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assert counts = 2 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
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zero <= '1';
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zero <= '1';
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wait for TbPeriod;
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wait for TbPeriod;
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