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FPGA : Suppression délai inutile encodeurs

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Geoffrey Frogeye 2018-03-02 15:01:48 +01:00
parent 6082662c2d
commit 5c1ccbce93
2 changed files with 12 additions and 18 deletions
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28
fpga/hedm.vhd
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@ -20,7 +20,6 @@ entity hedm is
end hedm; end hedm;
architecture Behavioral of hedm is architecture Behavioral of hedm is
signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
begin begin
processInput : process(clk, reset) processInput : process(clk, reset)
@ -29,18 +28,10 @@ begin
if reset = '1' then if reset = '1' then
counter := 0; counter := 0;
counts <= 0; counts <= 0;
An <= '0';
Bn <= '0';
Ap <= '0'; Ap <= '0';
Bp <= '0'; Bp <= '0';
elsif rising_edge(clk) then elsif rising_edge(clk) then
Ap <= An;
Bp <= Bn;
An <= chA;
Bn <= chB;
if zero = '1' then if zero = '1' then
counter := 0; counter := 0;
end if; end if;
@ -49,32 +40,35 @@ begin
-- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un -- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
-- tout aussi bon travail, on garde donc le code suivant pour la lisibilité -- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
if (Ap = '0' and An = '1') then -- Front montant A if (Ap = '0' and chA = '1') then -- Front montant A
if (Bn = '0') then if (chB = '0') then
counter := counter + 1; counter := counter + 1;
else else
counter := counter - 1; counter := counter - 1;
end if; end if;
elsif (Ap = '1' and An = '0') then -- Front descendant A elsif (Ap = '1' and chA = '0') then -- Front descendant A
if (Bn = '1') then if (chB = '1') then
counter := counter + 1; counter := counter + 1;
else else
counter := counter - 1; counter := counter - 1;
end if; end if;
elsif (Bp = '0' and Bn = '1') then -- Front montant B elsif (Bp = '0' and chB = '1') then -- Front montant B
if (An = '1') then if (chA = '1') then
counter := counter + 1; counter := counter + 1;
else else
counter := counter - 1; counter := counter - 1;
end if; end if;
elsif (Bp = '1' and Bn = '0') then -- Front descendant B elsif (Bp = '1' and chB = '0') then -- Front descendant B
if (An = '0') then if (chA = '0') then
counter := counter + 1; counter := counter + 1;
else else
counter := counter - 1; counter := counter - 1;
end if; end if;
end if; end if;
Ap <= chA;
Bp <= chB;
counts <= counter; counts <= counter;
end if; end if;

2
fpga/hedm_tb.vhd
View file

@ -112,7 +112,7 @@ begin
wait for TbPeriod; wait for TbPeriod;
wait for 5 * TbPeriod; wait for 5 * TbPeriod;
assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error; assert counts = 2 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
zero <= '1'; zero <= '1';
wait for TbPeriod; wait for TbPeriod;