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FPGA : Pipelinage du module de communication

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Geoffrey Frogeye 2018-02-28 16:00:12 +01:00
parent 68c7223fe4
commit 6013d6c9a9
5 changed files with 133 additions and 134 deletions
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7
fpga/Makefile
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@ -174,11 +174,14 @@ build/%.o: %.vhd
build/%_tb: build/%_tb.o $(addprefix build/,$(subst .vhd,.o,$(VHDSOURCE)))
ghdl -e $(GHDL_FLAGS) --workdir="$(shell dirname "$@")" -o "$(shell echo "$@" | tr A-Z a-z)" "$(basename $(notdir $<))"
%_test: build/%_tb
(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))")
build/%_tb.vcd: build/%_tb
(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --vcd="../$@" )
(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --vcd="../$@")
build/%_tb.ghw: build/%_tb
(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --wave="../$@" )
(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --wave="../$@")
%_wave: build/%_tb.ghw
gtkwave --save "$(notdir $(basename $<)).gtkw" "$<"