mirror of
https://github.com/RobotechLille/cdf2018-principal
synced 2024-11-21 15:46:06 +01:00
FPGA : Filtre
This commit is contained in:
parent
63b89e64b2
commit
68c7223fe4
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@ -166,13 +166,13 @@ isimgui: build/isim_$(TB)$(EXE)
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GHDL_FLAGS=--mb-comments
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%_syntax: %.vhd
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ghdl -s --mb-comments "$<"
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ghdl -s $(GHDL_FLAGS) "$<"
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build/%.o: %.vhd
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ghdl -a $(GHDL_FLAGS) --workdir="$(shell dirname "$@")" "$<"
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build/%_tb: build/%_tb.o $(addprefix build/,$(subst .vhd,.o,$(VHDSOURCE)))
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ghdl -e --workdir="$(shell dirname "$@")" -o "$(shell echo "$@" | tr A-Z a-z)" "$(basename $(notdir $<))"
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ghdl -e $(GHDL_FLAGS) --workdir="$(shell dirname "$@")" -o "$(shell echo "$@" | tr A-Z a-z)" "$(basename $(notdir $<))"
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build/%_tb.vcd: build/%_tb
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(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --vcd="../$@" )
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@ -44,9 +44,13 @@ architecture Behavioral of Principal is
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);
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end component;
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-- Sensors
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-- Distance sensors
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signal front : integer := 0;
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signal frontRaw : integer := 0;
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signal frontFinished : std_logic;
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signal back : integer := 0;
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signal backRaw : integer := 0;
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signal backFinished : std_logic;
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component hcsr04 IS
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generic(
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fFpga : INTEGER := fFpga
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@ -61,6 +65,16 @@ architecture Behavioral of Principal is
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finished : OUT STD_LOGIC
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);
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end component;
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component fir is
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Port (
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clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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signalIn : in INTEGER;
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signalOut : out INTEGER;
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start : in STD_LOGIC;
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done : out STD_LOGIC
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);
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end component;
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-- AF
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component uart is
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@ -127,25 +141,44 @@ begin
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zero => zerocoder,
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counts => right
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);
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frontCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => FRONTECHO,
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distance => front,
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distance => frontRaw,
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trigger => FRONTTRIGGER,
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start => '1'
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-- finished =>
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start => '1',
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finished => frontFinished
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);
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frontFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => frontRaw,
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signalOut => front,
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start => frontFinished
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-- done => done
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);
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backCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => BACKECHO,
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distance => back,
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distance => backRaw,
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trigger => BACKTRIGGER,
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start => '1'
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-- finished =>
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start => '1',
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finished => backFinished
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);
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backFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => backRaw,
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signalOut => back,
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start => backFinished
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-- done => done
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);
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FA: uart port map(
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clock => CLK,
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72
fpga/fir.vhd
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72
fpga/fir.vhd
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@ -0,0 +1,72 @@
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-- Code original écrit par Geoffrey Preud'homme et Eloi Zalczer
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-- dans le cadre du tutorat de Circuits Numériques Programmables du S7
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-- Filtre à réponse impulsionelle finie
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity fir is
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Port (
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clock : in STD_LOGIC; -- Afin de générer l'impulsion terminée
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reset : in STD_LOGIC;
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signalIn : in INTEGER; -- Signal d'entrée (un à la fois)
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signalOut : out INTEGER := 0; -- Signal filtré de sortie
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start : in STD_LOGIC; -- Lance une étape de filtrage
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done : out STD_LOGIC -- Signale la fin de l'étape de filtrage
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);
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end fir;
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architecture Behavioral of fir is
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constant N : INTEGER := 4; -- Nombre de coefficients
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constant M : INTEGER := 2**6; -- Facteur multiplicatif
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type INT_ARRAY is array (N-1 downto 0) of integer;
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constant coefficients : INT_ARRAY := (16,16,16,16);
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-- ↑ Coefficients du fir multipliés par M
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signal echantillons : INT_ARRAY := (others => 0); -- stockage des entrées retardées
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type fir_states is (waiting, calculating); -- machine à états finis
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signal state : fir_states := waiting;
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signal k : integer := 0;
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signal somme : integer := 0;
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begin
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filter: PROCESS(clock)
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begin
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if reset = '1' then
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done <= '0';
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state <= waiting;
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echantillons <= (others => 0);
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elsif rising_edge(clock) then
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if state = waiting then
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done <= '0';
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-- Quand start est à 1, on lance le filtre
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if start = '1' then
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-- Décalage
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echantillons(N-1 downto 1) <= echantillons(N-2 downto 0);
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echantillons(0) <= signalIn;
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k <= 0;
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somme <= 0;
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state <= calculating;
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end if;
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elsif state = calculating then
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-- Calcul de la somme
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somme <= somme + echantillons(k) * coefficients(k);
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k <= k + 1;
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if k = N-1 then
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-- Division par le facteur
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signalOut <= somme / M;
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done <= '1';
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state <= waiting;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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43
fpga/fir_tb.gtkw
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43
fpga/fir_tb.gtkw
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@ -0,0 +1,43 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Wed Feb 28 09:53:14 2018
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[*]
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[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/fir_tb.ghw"
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[dumpfile_mtime] "Wed Feb 28 09:53:10 2018"
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[dumpfile_size] 595494
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[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/fir_tb.gtkw"
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[timestart] 0
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[size] 1600 862
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[pos] -1 -1
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*-36.330536 375700000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.fir_tb.
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[sst_width] 213
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[signals_width] 177
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[sst_expanded] 1
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[sst_vpaned_height] 244
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@28
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top.fir_tb.clock
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top.fir_tb.reset
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[color] 1
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top.fir_tb.start
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@8420
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[color] 1
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top.fir_tb.signalin
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@420
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[color] 2
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top.fir_tb.dut.state
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@8420
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[color] 2
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top.fir_tb.dut.k
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@8421
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[color] 2
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top.fir_tb.dut.somme
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@28
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[color] 1
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top.fir_tb.done
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@8420
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[color] 1
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top.fir_tb.signalout
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[pattern_trace] 1
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[pattern_trace] 0
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92
fpga/fir_tb.vhd
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92
fpga/fir_tb.vhd
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@ -0,0 +1,92 @@
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-- Testbench automatically generated online
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-- at http://vhdl.lapinoo.net
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-- Generation date : 28.2.2018 08:45:52 GMT
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity fir_tb is
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end fir_tb;
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architecture tb of fir_tb is
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component FIR
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port (clock : in std_logic;
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reset : in std_logic;
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signalIn : in integer;
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signalOut : out integer;
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start : in std_logic;
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done : out std_logic);
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end component;
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signal clock : std_logic;
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signal reset : std_logic;
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signal signalIn : integer;
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signal signalOut : integer;
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signal start : std_logic;
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signal done : std_logic;
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constant TbPeriod : time := 20 ns;
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signal TbClock : std_logic := '0';
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signal TbSimEnded : std_logic := '0';
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constant SignalPeriod : time := 100 us;
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constant SignalAmpl : integer := 1000;
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constant SamplingPeriod : time := TbPeriod * 150;
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constant TimeBase : time := 1 ns; -- For working with integers when generating the signal
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begin
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dut : FIR
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port map (clock => clock,
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reset => reset,
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signalIn => signalIn,
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signalOut => signalOut,
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start => start,
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done => done);
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-- Clock generation
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TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
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clock <= TbClock;
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sampling : process
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variable nowI : integer;
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variable SignalPeriodI : integer;
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variable x : integer;
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variable y : integer;
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variable z : integer;
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begin
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while TbSimEnded = '0' loop
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-- Not optimised at all... No worries though it's just a testbench
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nowI := now / TimeBase;
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SignalPeriodI := SignalPeriod / TimeBase;
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x := nowI rem SignalPeriodI;
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y := x * SignalAmpl;
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z := y / SignalPeriodI;
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signalIn <= z;
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start <= '1';
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wait for TbPeriod;
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start <= '0';
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wait for SamplingPeriod - TbPeriod;
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end loop;
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wait;
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end process;
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stimuli : process
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begin
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-- Reset generation
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reset <= '1';
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wait for 100 ns;
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reset <= '0';
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wait for 100 ns;
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wait for 5 * SignalPeriod;
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-- Stop the clock and hence terminate the simulation
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TbSimEnded <= '1';
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wait;
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end process;
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end tb;
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@ -5,5 +5,5 @@ PROGRAMMER = mercpcl
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TOPLEVEL = Principal
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# Prod
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VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd
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VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd fir.vhd
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CONSTRAINTS = principal.ucf
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