mirror of
https://github.com/RobotechLille/cdf2018-principal
synced 2024-11-24 17:16:04 +01:00
FPGA : Gestion des encodeurs
This commit is contained in:
parent
23ef0c57dc
commit
d111629b12
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@ -28,9 +28,6 @@
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// Pour le debug
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#define A2FD_PING 'P'
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// Réinitialise la valeur des codeuses
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#define A2FD_RESETCODER 'R'
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// FPGA → Arduino
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// Erreur quelconque
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@ -175,10 +175,10 @@ build/%_tb: build/%_tb.o $(addprefix build/,$(subst .vhd,.o,$(VHDSOURCE)))
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ghdl -e --workdir="$(shell dirname "$@")" -o "$(shell echo "$@" | tr A-Z a-z)" "$(basename $(notdir $<))"
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build/%_tb.vcd: build/%_tb
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(cd "$(shell dirname "$<")"; ghdl -r "$(basename $(notdir $<))" --vcd="../$@" )
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(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --vcd="../$@" )
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build/%_tb.ghw: build/%_tb
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(cd "$(shell dirname "$<")"; ghdl -r "$(basename $(notdir $<))" --wave="../$@" )
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(cd "$(shell dirname "$<")"; time ghdl -r "$(basename $(notdir $<))" --wave="../$@" )
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%_wave: build/%_tb.ghw
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gtkwave --save "$(notdir $(basename $<)).gtkw" "$<"
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@ -6,8 +6,9 @@ use IEEE.NUMERIC_STD.ALL;
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entity Principal is
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Port ( CLK : in STD_LOGIC; -- Clock
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BTN : in STD_LOGIC; -- Reset
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-- FA
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IO : inout STD_LOGIC_VECTOR (21 downto 20);
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-- FA & Encoder
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IO : inout STD_LOGIC_VECTOR (21 downto 16);
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-- Debug
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LED : out STD_LOGIC_VECTOR (3 downto 0);
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AN : out STD_LOGIC_VECTOR (3 downto 0);
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@ -27,10 +28,22 @@ architecture Behavioral of Principal is
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-- Encoder
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signal left : integer;
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signal right : integer;
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signal zerocoder : std_logic;
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component hedm is
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Port (
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clk : in STD_LOGIC;
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chA : in STD_LOGIC;
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chB : in STD_LOGIC;
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reset : in STD_LOGIC;
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zero : in STD_LOGIC;
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counts : out integer
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);
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end component;
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-- Sensors
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signal front : integer;
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signal back : integer;
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signal front : integer := 0;
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signal back : integer := 0;
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-- AF
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component uart is
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@ -67,6 +80,7 @@ architecture Behavioral of Principal is
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reset : in std_logic;
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left : in integer;
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right : in integer;
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zerocoder : out std_logic;
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front : in integer;
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back : in integer;
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txData : out std_logic_vector(7 downto 0);
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@ -93,6 +107,24 @@ begin
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reset <= BTN;
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leftCoder: hedm port map (
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clk => CLK,
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chA => IO(19),
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chB => IO(18),
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reset => reset,
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zero => zerocoder,
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counts => left
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);
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rightCoder: hedm port map (
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clk => CLK,
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chA => IO(17),
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chB => IO(16),
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reset => reset,
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zero => zerocoder,
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counts => right
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);
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FA: uart port map(
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clock => CLK,
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reset => reset,
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@ -110,6 +142,7 @@ begin
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reset => reset,
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left => left,
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right => right,
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zerocoder => zerocoder,
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front => front,
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back => back,
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txData => txData,
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@ -126,6 +159,8 @@ begin
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if reset = '1' then
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count <= 0;
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theled <= "0000";
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front <= 0;
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back <= 0;
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elsif CLK'event and CLK = '1' then
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if count = 9999999 then
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count <= 0;
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@ -1,62 +1,80 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Sun Feb 25 14:12:54 2018
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[*] Tue Feb 27 09:39:06 2018
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[*]
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[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.vcd"
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[dumpfile_mtime] "Sun Feb 25 14:10:51 2018"
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[dumpfile_size] 38271255
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[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/Principal_tb.ghw"
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[dumpfile_mtime] "Tue Feb 27 09:38:56 2018"
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[dumpfile_size] 32911228
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[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/Principal_tb.gtkw"
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[timestart] 0
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[size] 1680 1012
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[size] 1600 862
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[pos] -1 -1
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*-40.000000 3481820000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] dut.
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*-41.636795 7980000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.principal_tb.
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[treeopen] top.principal_tb.dut.
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[treeopen] top.principal_tb.dut.fa.
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[sst_width] 213
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[signals_width] 198
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[sst_expanded] 1
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[sst_vpaned_height] 296
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@28
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[color] 4
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clk
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dut.reset
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top.principal_tb.dut.clk
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top.principal_tb.dut.reset
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[color] 2
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dut.fa.rx_baud_tick
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top.principal_tb.dut.fa.rx_baud_tick
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[color] 2
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dut.fa.rx
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top.principal_tb.dut.fa.rx
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@8028
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[color] 2
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dut.fa.uart_rx_count[2:0]
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#{top.principal_tb.dut.fa.uart_rx_count[2:0]} top.principal_tb.dut.fa.uart_rx_count[2] top.principal_tb.dut.fa.uart_rx_count[1] top.principal_tb.dut.fa.uart_rx_count[0]
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@22
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[color] 2
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dut.fa.uart_rx_data_vec[7:0]
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dut.rxdata[7:0]
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[color] 1
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#{top.principal_tb.dut.rxdata[7:0]} top.principal_tb.dut.rxdata[7] top.principal_tb.dut.rxdata[6] top.principal_tb.dut.rxdata[5] top.principal_tb.dut.rxdata[4] top.principal_tb.dut.rxdata[3] top.principal_tb.dut.rxdata[2] top.principal_tb.dut.rxdata[1] top.principal_tb.dut.rxdata[0]
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@820
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dut.rxdata[7:0]
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[color] 1
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#{top.principal_tb.dut.rxdata[7:0]} top.principal_tb.dut.rxdata[7] top.principal_tb.dut.rxdata[6] top.principal_tb.dut.rxdata[5] top.principal_tb.dut.rxdata[4] top.principal_tb.dut.rxdata[3] top.principal_tb.dut.rxdata[2] top.principal_tb.dut.rxdata[1] top.principal_tb.dut.rxdata[0]
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@28
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dut.rxstb
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@420
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[color] 5
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dut.com.readoffset
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[color] 5
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dut.com.sendoffset
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[color] 1
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top.principal_tb.dut.com.rxstb
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@22
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[color] 4
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dut.txdata[7:0]
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[color] 1
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#{top.principal_tb.dut.txdata[7:0]} top.principal_tb.dut.txdata[7] top.principal_tb.dut.txdata[6] top.principal_tb.dut.txdata[5] top.principal_tb.dut.txdata[4] top.principal_tb.dut.txdata[3] top.principal_tb.dut.txdata[2] top.principal_tb.dut.txdata[1] top.principal_tb.dut.txdata[0]
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@820
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[color] 4
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dut.txdata[7:0]
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[color] 1
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#{top.principal_tb.dut.txdata[7:0]} top.principal_tb.dut.txdata[7] top.principal_tb.dut.txdata[6] top.principal_tb.dut.txdata[5] top.principal_tb.dut.txdata[4] top.principal_tb.dut.txdata[3] top.principal_tb.dut.txdata[2] top.principal_tb.dut.txdata[1] top.principal_tb.dut.txdata[0]
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@28
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dut.txstb
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dut.txack
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[color] 1
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top.principal_tb.dut.txstb
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[color] 1
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top.principal_tb.dut.txack
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[color] 2
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dut.fa.tx
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[color] 2
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dut.fa.tx_baud_tick
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top.principal_tb.dut.fa.tx_baud_tick
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@8028
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[color] 2
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dut.fa.uart_tx_count[2:0]
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#{top.principal_tb.dut.fa.uart_tx_count[2:0]} top.principal_tb.dut.fa.uart_tx_count[2] top.principal_tb.dut.fa.uart_tx_count[1] top.principal_tb.dut.fa.uart_tx_count[0]
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@22
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[color] 2
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dut.fa.uart_tx_data_vec[7:0]
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#{top.principal_tb.dut.fa.uart_tx_data_vec[7:0]} top.principal_tb.dut.fa.uart_tx_data_vec[7] top.principal_tb.dut.fa.uart_tx_data_vec[6] top.principal_tb.dut.fa.uart_tx_data_vec[5] top.principal_tb.dut.fa.uart_tx_data_vec[4] top.principal_tb.dut.fa.uart_tx_data_vec[3] top.principal_tb.dut.fa.uart_tx_data_vec[2] top.principal_tb.dut.fa.uart_tx_data_vec[1] top.principal_tb.dut.fa.uart_tx_data_vec[0]
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@28
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[color] 2
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top.principal_tb.dut.fa.tx
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[color] 6
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top.principal_tb.dut.zerocoder
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[color] 6
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top.principal_tb.dut.leftcoder.cha
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[color] 6
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top.principal_tb.dut.leftcoder.chb
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@8420
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[color] 6
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top.principal_tb.dut.left
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@28
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[color] 6
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top.principal_tb.dut.rightcoder.cha
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[color] 6
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top.principal_tb.dut.rightcoder.chb
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@8421
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[color] 6
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top.principal_tb.dut.right
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[pattern_trace] 1
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[pattern_trace] 0
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@ -6,14 +6,14 @@ library ieee;
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use ieee.std_logic_1164.all;
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entity Principal_tb is
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end Principal_tb;
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end Principal_tb;
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architecture tb of Principal_tb is
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component Principal
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port (CLK : in std_logic;
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BTN : in std_logic;
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IO : inout std_logic_vector (21 downto 20);
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IO : inout std_logic_vector (21 downto 16);
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LED : out std_logic_vector (3 downto 0);
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AN : out std_logic_vector (3 downto 0);
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A_TO_G : out std_logic_vector (6 downto 0);
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@ -22,7 +22,7 @@ architecture tb of Principal_tb is
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signal CLK : std_logic;
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signal BTN : std_logic;
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signal IO : std_logic_vector (21 downto 20);
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signal IO : std_logic_vector (21 downto 16);
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signal LED : std_logic_vector (3 downto 0);
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signal AN : std_logic_vector (3 downto 0);
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signal A_TO_G : std_logic_vector (6 downto 0);
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@ -36,6 +36,8 @@ architecture tb of Principal_tb is
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constant CharacterPeriod : time := 10 * BaudPeriod;
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signal rx : std_logic;
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signal tx : std_logic;
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constant CoderPeriod : time := 27611 ns;
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begin
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dut : Principal
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@ -55,9 +57,49 @@ begin
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IO(20) <= rx;
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tx <= IO(21);
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leftCoder : process
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begin
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while TbSimEnded = '0' loop
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IO(19) <= '1';
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wait for CoderPeriod;
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IO(18) <= '1';
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wait for CoderPeriod;
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IO(19) <= '0';
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wait for CoderPeriod;
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IO(18) <= '0';
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wait for CoderPeriod;
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end loop;
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wait;
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end process;
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rightCoder : process
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begin
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while TbSimEnded = '0' loop
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IO(16) <= '0';
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wait for CoderPeriod;
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IO(17) <= '0';
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wait for CoderPeriod;
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IO(16) <= '1';
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wait for CoderPeriod;
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IO(17) <= '1';
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wait for CoderPeriod;
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end loop;
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wait;
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end process;
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stimuli : process
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variable sending : std_logic_vector(7 downto 0);
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procedure send
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(char : std_logic_vector(7 downto 0)) is
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begin
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rx <= '0'; -- Start bit
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wait for BaudPeriod;
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for I in 0 to 7 loop
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rx <= char(I);
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wait for BaudPeriod;
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end loop;
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rx <= '1'; -- Stop bit
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wait for BaudPeriod;
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end procedure;
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begin
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rx <= '1';
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@ -69,40 +111,39 @@ begin
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wait for 2 * BaudPeriod;
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-- Send 'P'
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rx <= '0'; -- Start bit
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sending := x"50"; -- 'P'
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wait for BaudPeriod;
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for I in 0 to 7 loop
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rx <= sending(I);
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wait for BaudPeriod;
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end loop;
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rx <= '1'; -- Stop bit
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wait for BaudPeriod;
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-- Wait for 1 byte receive
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-- Send 'P'
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send(x"50"); -- 'P'
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wait for CharacterPeriod;
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-- Wait margin
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wait for 2 * BaudPeriod;
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-- Send '?'
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rx <= '0'; -- Start bit
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sending := x"3F"; -- '?'
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wait for BaudPeriod;
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for I in 0 to 7 loop
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rx <= sending(I);
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wait for BaudPeriod;
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end loop;
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rx <= '1'; -- Stop bit
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wait for BaudPeriod;
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-- Wait for 2 bytes receive
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-- Send '?'
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send(x"3F"); -- '?'
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wait for 2 * CharacterPeriod;
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-- Wait margin
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wait for 2 * BaudPeriod;
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-- Send 'C'
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send(x"43"); -- '?'
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wait for 5 * CharacterPeriod;
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-- Wait margin
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wait for 5 * BaudPeriod;
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-- Send 'D'
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send(x"44"); -- '?'
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wait for 5 * CharacterPeriod;
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-- Wait margin
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wait for 5 * BaudPeriod;
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-- Stop the clock and hence terminate the simulation
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TbSimEnded <= '1';
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wait;
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@ -9,6 +9,7 @@ entity communication is
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reset : in std_logic;
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left : in integer;
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right : in integer;
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zerocoder : out std_logic;
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front : in integer;
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back : in integer;
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txData : out std_logic_vector(7 downto 0);
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@ -30,7 +31,7 @@ architecture Behavioral of communication is
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constant F2AT_CAPT : std_logic_vector(7 downto 0) := x"63"; -- 'c'
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type readStates is (readIdle);
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signal readState : readStates := readIdle;
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signal readState : readStates := readIdle; -- TODO Make sure is correctly reset when reworking this
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signal readOffset : integer := 0;
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type sendMessages is (none, A2FD_PINGs, F2AI_CODERs, F2AI_CAPTs, F2AD_ERR_UNKNOWN_CODEs);
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@ -91,8 +92,20 @@ begin
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begin
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if reset = '1' then
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readState <= readIdle;
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sendMessage := none;
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sendOffset := 0;
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sendSize := 0;
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sendTail := 0;
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sendHead := 0;
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sendLooped := false;
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frontTrigger <= 0;
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backTrigger <= 0;
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zerocoder <= '0';
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txData <= x"00";
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else
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if rising_edge(clock) then
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zerocoder <= '0';
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-- If read something
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if rxStb = '1' then
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if readState = readIdle then
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@ -120,9 +133,15 @@ begin
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sendSize := 1;
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when F2AI_CAPTs =>
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sendData(7 downto 0) := F2AI_CAPT;
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sendData(23 downto 8) := std_logic_vector(to_unsigned(front, 16));
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sendData(23 downto 8) := std_logic_vector(to_signed(front, 16));
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sendData(39 downto 24) := std_logic_vector(to_unsigned(back, 16));
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sendSize := 5;
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when F2AI_CODERs =>
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zerocoder <= '1';
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sendData(7 downto 0) := F2AI_CODER;
|
||||
sendData(23 downto 8) := std_logic_vector(to_signed(left, 16));
|
||||
sendData(39 downto 24) := std_logic_vector(to_signed(right, 16));
|
||||
sendSize := 5;
|
||||
when others => -- Including F2AD_ERR_UNKNOWN_CODEs
|
||||
sendData(7 downto 0) := F2AD_ERR;
|
||||
sendData(15 downto 8) := ERR_UNKNOWN_CODE;
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
|
||||
[*] Mon Feb 26 19:15:08 2018
|
||||
[*] Tue Feb 27 08:58:38 2018
|
||||
[*]
|
||||
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/communication_tb.ghw"
|
||||
[dumpfile_mtime] "Mon Feb 26 19:15:01 2018"
|
||||
[dumpfile_size] 4519
|
||||
[dumpfile_mtime] "Tue Feb 27 08:58:14 2018"
|
||||
[dumpfile_size] 5411
|
||||
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/communication_tb.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1600 862
|
||||
[pos] -1 -1
|
||||
*-29.277596 1395000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
*-29.549107 930000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.communication_tb.
|
||||
[treeopen] top.communication_tb.dut.
|
||||
|
|
@ -45,5 +45,8 @@ top.communication_tb.dut.readoffset
|
|||
top.communication_tb.dut.txstb
|
||||
[color] 1
|
||||
top.communication_tb.dut.txack
|
||||
@29
|
||||
[color] 2
|
||||
top.communication_tb.dut.zerocoder
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ architecture tb of communication_tb is
|
|||
left : in integer;
|
||||
right : in integer;
|
||||
front : in integer;
|
||||
zerocoder : out std_logic;
|
||||
back : in integer;
|
||||
txData : out std_logic_vector (7 downto 0);
|
||||
txStb : out std_logic;
|
||||
|
|
@ -33,6 +34,7 @@ architecture tb of communication_tb is
|
|||
signal back : integer;
|
||||
signal txData : std_logic_vector (7 downto 0);
|
||||
signal txStb : std_logic;
|
||||
signal zerocoder : std_logic;
|
||||
signal txAck : std_logic;
|
||||
signal rxData : std_logic_vector (7 downto 0);
|
||||
signal rxStb : std_logic;
|
||||
|
|
@ -54,6 +56,7 @@ begin
|
|||
back => back,
|
||||
txData => txData,
|
||||
txStb => txStb,
|
||||
zerocoder => zerocoder,
|
||||
txAck => txAck,
|
||||
rxData => rxData,
|
||||
rxStb => rxStb);
|
||||
|
|
@ -92,7 +95,6 @@ begin
|
|||
assert txData = x"50" report "Not sent 'P'" severity error;
|
||||
assert txStb = '1' report "Not sending" severity error;
|
||||
|
||||
report "Acknowledging send" severity note;
|
||||
wait for 100 ns;
|
||||
txAck <= '1';
|
||||
wait for TbPeriod;
|
||||
|
|
@ -115,7 +117,6 @@ begin
|
|||
assert txData = x"45" report "Not sent 'E'" severity error;
|
||||
assert txStb = '1' report "Not sending" severity error;
|
||||
|
||||
report "Acknowledging send" severity note;
|
||||
wait for 100 ns;
|
||||
txAck <= '1';
|
||||
wait for TbPeriod;
|
||||
|
|
@ -125,7 +126,6 @@ begin
|
|||
assert txData = x"43" report "Not sent 'C'" severity error;
|
||||
assert txStb = '1' report "Not sending" severity error;
|
||||
|
||||
report "Acknowledging send" severity note;
|
||||
wait for 100 ns;
|
||||
txAck <= '1';
|
||||
wait for TbPeriod;
|
||||
|
|
@ -150,7 +150,6 @@ begin
|
|||
assert txData = x"50" report "Not sent 'P'" severity error;
|
||||
assert txStb = '1' report "Not sending" severity error;
|
||||
|
||||
report "Acknowledging send" severity note;
|
||||
wait for 100 ns;
|
||||
txAck <= '1';
|
||||
wait for TbPeriod;
|
||||
|
|
@ -176,7 +175,36 @@ begin
|
|||
assert txData = shouldReceive(I) report "Not sent correct data, got " & integer'image(to_integer(unsigned(txData))) & ", expected " & integer'image(to_integer(unsigned(shouldReceive(I))))severity error;
|
||||
assert txStb = '1' report "Not sending" severity error;
|
||||
|
||||
report "Acknowledging send" severity note;
|
||||
wait for 100 ns;
|
||||
txAck <= '1';
|
||||
wait for TbPeriod;
|
||||
txAck <= '0';
|
||||
end loop;
|
||||
|
||||
wait for 100 ns;
|
||||
assert txStb = '0' report "Not stopping send" severity error;
|
||||
|
||||
-- Test encoder
|
||||
left <= 1152;
|
||||
right <= 11614;
|
||||
|
||||
report "TEST Receiving 'D'" severity note;
|
||||
rxData <= x"44";
|
||||
rxStb <= '1';
|
||||
wait for TbPeriod;
|
||||
assert zerocoder = '1' report "Not reseting coder values" severity error;
|
||||
left <= 0;
|
||||
right <= 0;
|
||||
rxStb <= '0';
|
||||
wait for TbPeriod;
|
||||
assert zerocoder = '0' report "Not stopping reseting coder values" severity error;
|
||||
|
||||
shouldReceive(0 to 4) := (x"44", x"80", x"04", x"5E", x"2D");
|
||||
for I in 0 to 4 loop
|
||||
wait for 100 ns;
|
||||
assert txData = shouldReceive(I) report "Not sent correct data, got " & integer'image(to_integer(unsigned(txData))) & ", expected " & integer'image(to_integer(unsigned(shouldReceive(I))))severity error;
|
||||
assert txStb = '1' report "Not sending" severity error;
|
||||
|
||||
wait for 100 ns;
|
||||
txAck <= '1';
|
||||
wait for TbPeriod;
|
||||
|
|
|
|||
|
|
@ -13,20 +13,22 @@ entity hedm is
|
|||
clk : in STD_LOGIC; -- Horloge, la fréquence n'importe pas
|
||||
chA : in STD_LOGIC; -- Canal A
|
||||
chB : in STD_LOGIC; -- Canal B
|
||||
reset : in STD_LOGIC;
|
||||
reset : in STD_LOGIC; -- Hard reset
|
||||
zero : in STD_LOGIC; -- Force la valeur à zéro sans réinitialiser le fonctionnement
|
||||
counts : out integer
|
||||
);
|
||||
end hedm;
|
||||
|
||||
architecture Behavioral of hedm is
|
||||
signal counter : integer := 0;
|
||||
signal An, Bn : STD_LOGIC := '0'; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
|
||||
signal Ap, Bp : STD_LOGIC := '0'; -- Précédentes valeurs de A et B pour détecter les front montant
|
||||
begin
|
||||
processInput : process(clk, reset)
|
||||
variable counter : integer := 0;
|
||||
begin
|
||||
if reset = '1' then
|
||||
counter <= 0;
|
||||
counter := 0;
|
||||
counts <= 0;
|
||||
An <= '0';
|
||||
Bn <= '0';
|
||||
Ap <= '0';
|
||||
|
|
@ -39,39 +41,44 @@ begin
|
|||
An <= chA;
|
||||
Bn <= chB;
|
||||
|
||||
if zero = '1' then
|
||||
counter := 0;
|
||||
end if;
|
||||
|
||||
-- On pourrait optimiser la logique avec un tableau de Karnaugh ou autres méthodes
|
||||
-- de simplification d'algèbre de Boole, mais le synthétiseur pour FPGA fera un
|
||||
-- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
|
||||
|
||||
if (Ap = '0' and An = '1') then -- Front montant A
|
||||
if (Bn = '0') then
|
||||
counter <= counter + 1;
|
||||
counter := counter + 1;
|
||||
else
|
||||
counter <= counter - 1;
|
||||
counter := counter - 1;
|
||||
end if;
|
||||
elsif (Ap = '1' and An = '0') then -- Front descendant A
|
||||
if (Bn = '1') then
|
||||
counter <= counter + 1;
|
||||
counter := counter + 1;
|
||||
else
|
||||
counter <= counter - 1;
|
||||
counter := counter - 1;
|
||||
end if;
|
||||
elsif (Bp = '0' and Bn = '1') then -- Front montant B
|
||||
if (An = '1') then
|
||||
counter <= counter + 1;
|
||||
counter := counter + 1;
|
||||
else
|
||||
counter <= counter - 1;
|
||||
counter := counter - 1;
|
||||
end if;
|
||||
elsif (Bp = '1' and Bn = '0') then -- Front descendant B
|
||||
if (An = '0') then
|
||||
counter <= counter + 1;
|
||||
counter := counter + 1;
|
||||
else
|
||||
counter <= counter - 1;
|
||||
counter := counter - 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
counts <= counter;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
counts <= counter;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,25 +1,43 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
|
||||
[*] Sat Feb 24 16:20:02 2018
|
||||
[*] Tue Feb 27 08:32:01 2018
|
||||
[*]
|
||||
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.vcd"
|
||||
[dumpfile_mtime] "Sat Feb 24 16:19:31 2018"
|
||||
[dumpfile_size] 10717
|
||||
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.gtkw"
|
||||
[dumpfile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/build/hedm_tb.ghw"
|
||||
[dumpfile_mtime] "Tue Feb 27 08:31:12 2018"
|
||||
[dumpfile_size] 4287
|
||||
[savefile] "/home/geoffrey/Documents/Polytech/Robotech/2017-2018/CdF/cdf2018-principal/fpga/hedm_tb.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1600 862
|
||||
[pos] -1 -1
|
||||
*-28.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
*-28.781492 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.hedm_tb.
|
||||
[sst_width] 213
|
||||
[signals_width] 78
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 244
|
||||
@28
|
||||
clk
|
||||
reset
|
||||
cha
|
||||
chb
|
||||
@421
|
||||
counts
|
||||
top.hedm_tb.dut.clk
|
||||
top.hedm_tb.dut.reset
|
||||
[color] 4
|
||||
top.hedm_tb.dut.zero
|
||||
[color] 5
|
||||
top.hedm_tb.dut.cha
|
||||
[color] 5
|
||||
top.hedm_tb.dut.chb
|
||||
[color] 2
|
||||
top.hedm_tb.dut.ap
|
||||
[color] 2
|
||||
top.hedm_tb.dut.bp
|
||||
[color] 2
|
||||
top.hedm_tb.dut.an
|
||||
[color] 2
|
||||
top.hedm_tb.dut.bn
|
||||
@420
|
||||
[color] 1
|
||||
top.hedm_tb.dut.counts
|
||||
@8421
|
||||
[color] 1
|
||||
top.hedm_tb.dut.counts
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ architecture tb of hedm_tb is
|
|||
chA : in std_logic;
|
||||
chB : in std_logic;
|
||||
reset : in std_logic;
|
||||
zero : in std_logic;
|
||||
counts : out integer);
|
||||
end component;
|
||||
|
||||
|
|
@ -22,6 +23,7 @@ architecture tb of hedm_tb is
|
|||
signal chA : std_logic;
|
||||
signal chB : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal zero : std_logic;
|
||||
signal counts : integer;
|
||||
|
||||
constant TbPeriod : time := 20 ns;
|
||||
|
|
@ -35,6 +37,7 @@ begin
|
|||
chA => chA,
|
||||
chB => chB,
|
||||
reset => reset,
|
||||
zero => zero,
|
||||
counts => counts);
|
||||
|
||||
-- Clock generation
|
||||
|
|
@ -48,6 +51,7 @@ begin
|
|||
begin
|
||||
chA <= '0';
|
||||
chB <= '0';
|
||||
zero <= '0';
|
||||
|
||||
-- Reset generation
|
||||
reset <= '1';
|
||||
|
|
@ -70,8 +74,17 @@ begin
|
|||
wait for 5 * TbPeriod;
|
||||
assert counts = nbTours * 4 report "Sens avant faux, reçu " & integer'image(counts) severity error;
|
||||
|
||||
-- Test zero
|
||||
zero <= '1';
|
||||
wait for TbPeriod;
|
||||
zero <= '0';
|
||||
wait for TbPeriod;
|
||||
|
||||
-- Test sens avant
|
||||
wait for 5 * TbPeriod;
|
||||
assert counts = 0 report "Zero faux, reçu " & integer'image(counts) severity error;
|
||||
|
||||
|
||||
-- Test sens arrière
|
||||
for I in 0 to nbTours-1 loop
|
||||
chB <= '1';
|
||||
wait for TbPeriod;
|
||||
|
|
@ -84,7 +97,27 @@ begin
|
|||
end loop;
|
||||
|
||||
wait for 5 * TbPeriod;
|
||||
assert counts = 0 report "Sens arrière faux, reçu " & integer'image(counts) severity error;
|
||||
assert counts = -40 report "Sens arrière faux, reçu " & integer'image(counts) severity error;
|
||||
|
||||
-- Test zero en éxecution
|
||||
chA <= '1';
|
||||
wait for TbPeriod;
|
||||
chB <= '1';
|
||||
wait for TbPeriod;
|
||||
chA <= '0';
|
||||
zero <= '1';
|
||||
wait for TbPeriod;
|
||||
chB <= '0';
|
||||
zero <= '0';
|
||||
wait for TbPeriod;
|
||||
|
||||
wait for 5 * TbPeriod;
|
||||
assert counts = 3 report "Zero en éxecution faux, reçu " & integer'image(counts) severity error;
|
||||
|
||||
zero <= '1';
|
||||
wait for TbPeriod;
|
||||
zero <= '0';
|
||||
wait for TbPeriod;
|
||||
|
||||
-- Test aller-retours
|
||||
for I in 0 to nbTours-1 loop
|
||||
|
|
@ -102,6 +135,7 @@ begin
|
|||
assert counts = 0 report "Aller-retours faux, reçu " & integer'image(counts) severity error;
|
||||
|
||||
|
||||
|
||||
-- Stop the clock and hence terminate the simulation
|
||||
TbSimEnded <= '1';
|
||||
wait;
|
||||
|
|
|
|||
Loading…
Reference in a new issue