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https://github.com/RobotechLille/cdf2018-principal
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30 lines
648 B
VHDL
30 lines
648 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Principal is
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Port ( CLK : in STD_LOGIC;
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LED : out STD_LOGIC_VECTOR (3 downto 0));
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end Principal;
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architecture Behavioral of Principal is
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signal pulse : std_logic := '0';
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signal count : integer range 0 to 49999999 := 0;
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begin
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counter : process(CLK)
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begin
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if CLK'event and CLK = '1' then
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if count = 49999999 then
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count <= 0;
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pulse <= not pulse;
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else
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count <= count + 1;
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end if;
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end if;
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end process;
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LED(3 downto 0) <= (others => pulse);
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end Behavioral;
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