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Geoffrey Frogeye 2018-02-07 17:57:01 +01:00
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fpga/.gitignore vendored Normal file
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build/*

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# From https://github.com/duskwuff/Xilinx-ISE-Makefile
###########################################################################
## Xilinx ISE Makefile
##
## To the extent possible under law, the author(s) have dedicated all copyright
## and related and neighboring rights to this software to the public domain
## worldwide. This software is distributed without any warranty.
###########################################################################
include project.cfg
###########################################################################
# Default values
###########################################################################
ifndef XILINX
$(error XILINX must be defined)
endif
ifndef PROJECT
$(error PROJECT must be defined)
endif
ifndef TARGET_PART
$(error TARGET_PART must be defined)
endif
TOPLEVEL ?= $(PROJECT)
CONSTRAINTS ?= $(PROJECT).ucf
BITFILE ?= build/$(PROJECT).bit
COMMON_OPTS ?= -intstyle xflow
XST_OPTS ?=
NGDBUILD_OPTS ?=
MAP_OPTS ?=
PAR_OPTS ?=
BITGEN_OPTS ?=
TRACE_OPTS ?=
FUSE_OPTS ?= -incremental
PROGRAMMER ?= none
IMPACT_OPTS ?= -batch impact.cmd
DJTG_EXE ?= djtgcfg
DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
DJTG_INDEX ?= 0
XC3SPROG_EXE ?= xc3sprog
XC3SPROG_CABLE ?= none
XC3SPROG_OPTS ?=
MERCPCL_EXE ?= mercpcl
###########################################################################
# Internal variables, platform-specific definitions, and macros
###########################################################################
ifeq ($(OS),Windows_NT)
XILINX := $(shell cygpath -m $(XILINX))
CYG_XILINX := $(shell cygpath $(XILINX))
EXE := .exe
XILINX_PLATFORM ?= nt64
PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
else
EXE :=
XILINX_PLATFORM ?= lin64
PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
endif
TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
cd build && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
# isim executables don't work without this
export XILINX
###########################################################################
# Default build
###########################################################################
default: $(BITFILE)
clean:
rm -rf build
build/$(PROJECT).prj: project.cfg
@echo "Updating $@"
@mkdir -p build
@rm -f $@
@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
@cp build/$(PROJECT).prj $@
@$(foreach file,$(VTEST),echo "verilog work \"../$(file)\"" >> $@;)
@$(foreach file,$(VHDTEST),echo "vhdl work \"../$(file)\"" >> $@;)
@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
build/$(PROJECT).scr: project.cfg
@echo "Updating $@"
@mkdir -p build
@rm -f $@
@echo "run" \
"-ifn $(PROJECT).prj" \
"-ofn $(PROJECT).ngc" \
"-ifmt mixed" \
"$(XST_OPTS)" \
"-top $(TOPLEVEL)" \
"-ofmt NGC" \
"-p $(TARGET_PART)" \
> build/$(PROJECT).scr
$(BITFILE): project.cfg $(VSOURCE) $(VHDSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
@mkdir -p build
$(call RUN,xst) $(COMMON_OPTS) \
-ifn $(PROJECT).scr
$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
-p $(TARGET_PART) $(addprefix -uc ../,$(CONSTRAINTS)) \
$(PROJECT).ngc $(PROJECT).ngd
$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
-p $(TARGET_PART) \
-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
-w $(PROJECT).ncd $(PROJECT).bit
@echo -ne "\e[1;32m======== OK ========\e[m\n"
###########################################################################
# Testing (work in progress)
###########################################################################
trace: project.cfg $(BITFILE)
$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
$(PROJECT).ncd $(PROJECT).pcf
test: $(TEST_EXES)
build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST)
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
-prj $(PROJECT)_sim.prj \
-o isim_$*$(EXE) \
work.$* work.glbl
isim: build/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
@echo "run all" >> build/isim_$(TB).cmd
cd build ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
isimgui: build/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
@echo "run all" >> build/isim_$(TB).cmd
cd build ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
###########################################################################
# Programming
###########################################################################
ifeq ($(PROGRAMMER), impact)
prog: $(BITFILE)
$(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
endif
ifeq ($(PROGRAMMER), digilent)
prog: $(BITFILE)
$(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
endif
ifeq ($(PROGRAMMER), xc3sprog)
prog: $(BITFILE)
$(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
endif
ifeq ($(PROGRAMMER), mercpcl)
prog: $(BITFILE)
$(MERCPCL_EXE) $(BITFILE)
endif
ifeq ($(PROGRAMMER), none)
prog:
$(error PROGRAMMER must be set to use 'make prog')
endif
###########################################################################
# vim: set filetype=make: #

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Principal is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (3 downto 0));
end Principal;
architecture Behavioral of Principal is
signal pulse : std_logic := '0';
signal count : integer range 0 to 49999999 := 0;
begin
counter : process(CLK)
begin
if CLK'event and CLK = '1' then
if count = 49999999 then
count <= 0;
pulse <= not pulse;
else
count <= count + 1;
end if;
end if;
end process;
LED(3 downto 0) <= (others => pulse);
end Behavioral;

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# Programme pour le FPGA
Convention : les fichiers .vhd commençant par une minuscule sont des modules, ceux commençant par une majuscule peuvent être utilisés en top-level.

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY hcSr04 IS
GENERIC(
fFpga : INTEGER := 50_000_000 -- frequency of the FPGA clock (Hz)
);
PORT(
clk : IN STD_LOGIC; -- clock of the FPGA
echo : IN STD_LOGIC; -- echo pin of the hcSr04
distance : OUT INTEGER RANGE 0 TO 65535; -- Divide by 58 to get the value in cm
trigger : OUT STD_LOGIC; -- trigger pin of the hcSr04
start : IN STD_LOGIC; -- Set to '1' everytime a measurement is needed (or keep at '1' for continuous measurement)
finished : OUT STD_LOGIC -- Driven to '1' everytime a measurement has finished
);
END hcSr04;
ARCHITECTURE Behavioral OF hcSr04 IS
-- Generate us clock
CONSTANT fUs : INTEGER := 1_000_000; -- Frequency of the microsecond clock
CONSTANT usTicks : INTEGER := fFPGA / fUs; -- Number of FPGA tick that makes a microsecond
SIGNAL fpgaCounter : INTEGER RANGE 0 TO usTicks - 1; -- Count the microsecond
SIGNAL usClk : STD_LOGIC; -- Clock that ticks every us
-- Trigger
CONSTANT triggerDuration : INTEGER := 10; -- Number of us that makes up a trigger sequence
SIGNAL triggerCounter : INTEGER RANGE 0 TO triggerDuration - 1 := 0; -- Progress in the trigger sequence
SIGNAL theTrigger : STD_LOGIC := '0'; -- Trigger pin but with default value
-- Measurement
CONSTANT measurementDuration : INTEGER := 60_000; -- Number of us that makes up a measurement cycle
SIGNAL measurementCounter : INTEGER RANGE 0 TO measurementDuration - 1 := 0; -- Progress in the measurement cycle
-- Distance
SIGNAL distanceCounter : INTEGER RANGE 0 TO 65535 := 0; -- Distance measured (in us)
-- State machine
TYPE stateType IS (waiting, triggering, measuring);
SIGNAL state : stateType;
BEGIN
us : process(clk)
begin
if rising_edge(clk) then
if fpgaCounter = 0 then
usClk <= '0';
elsif fpgaCounter = 1 then
usClk <= '1';
end if;
fpgaCounter <= fpgaCounter + 1;
end if;
end process;
trigger <= theTrigger;
measure : process(usClk)
begin
if rising_edge(usClk) then
CASE state IS
WHEN waiting =>
finished <= '0';
IF start = '1' THEN
theTrigger <= '1';
triggerCounter <= 0;
state <= triggering;
END IF;
WHEN triggering =>
triggerCounter <= triggerCounter + 1;
IF triggerCounter = triggerDuration - 1 THEN
theTrigger <= '0';
measurementCounter <= 0;
distanceCounter <= 0;
state <= measuring;
END IF;
WHEN measuring =>
IF echo = '1' and distanceCounter < 65535 THEN
distanceCounter <= distanceCounter + 1;
END IF;
measurementCounter <= measurementCounter + 1;
IF measurementCounter = measurementDuration - 1 THEN
distance <= distanceCounter;
finished <= '1';
state <= waiting;
END IF;
END CASE;
end if;
end process;
END Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY hcSr04 IS
GENERIC(
fFpga : INTEGER := 50_000_000; -- frequency of the FPGA clock (Hz)
maxOutput : INTEGER := 65535 -- maximum number to store the distance
);
PORT(
clk : IN STD_LOGIC; -- clock of the FPGA
echo : IN STD_LOGIC; -- echo pin of the hcSr04
distance : OUT INTEGER RANGE 0 TO maxOutput; -- Ranges from 0 to 4 meters, 0 if no data
trigger : OUT STD_LOGIC; -- trigger pin of the hcSr04
start : IN STD_LOGIC; -- Set to '1' everytime a measurement is needed (or keep at '1' for continuous measurement)
finished : OUT STD_LOGIC -- Driven to '1' everytime a measurement has finished
);
END hcSr04;
ARCHITECTURE Behavioral OF hcSr04 IS
CONSTANT triggerTicks : INTEGER := fFPGA / 100000; -- Number of FPGA ticks that makes 10us (used for trigger)
CONSTANT measurementTicks : INTEGER := fFPGA / 17; -- Number of FPGA ticks that makes 60ms (used for measurement cycles)
CONSTANT maximumRange : INTEGER := 4; -- Maximum range the sensor can detect
CONSTANT distanceTicks : INTEGER := maximumRange * fFPGA / 172; -- Number of FPGA ticks that makes the maximum distance that can be measured
-- 172 = 1 / 58 s/m
SIGNAL measurementCounter : INTEGER RANGE 0 to measurementTicks - 1 := 0; -- Progress in the measurement
SIGNAL distanceCounter : INTEGER RANGE 0 to distanceTicks - 1 := 0; -- Ticks for wich echo has been at one
SIGNAL triggerCounter : INTEGER RANGE 0 to triggerTicks - 1 := 0; -- Progress in the trigger
TYPE stateType IS (init, waiting, triggering, measuring);
SIGNAL state : stateType;
BEGIN
measure : process(clk)
begin
if rising_edge(clk) then
CASE state IS
WHEN init =>
trigger <= '0';
distance <= 0;
state <= waiting;
WHEN waiting =>
finished <= '0';
IF start = '1' THEN
trigger <= '1';
triggerCounter <= 0;
state <= triggering;
END IF;
WHEN triggering =>
triggerCounter <= triggerCounter + 1;
IF triggerCounter = triggerTicks - 1 THEN
trigger <= '0';
measurementCounter <= 0;
distanceCounter <= 0;
state <= measuring;
END IF;
WHEN measuring =>
IF echo = '1' and distanceCounter < distanceTicks THEN
distanceCounter <= distanceCounter + 1;
END IF;
measurementCounter <= measurementCounter + 1;
IF measurementCounter = measurementTicks - 1 THEN
distance <= distanceCounter * maxOutput / distanceTicks;
finished <= '1';
state <= waiting;
END IF;
END CASE;
end if;
end process;
END Behavioral;

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-- Process signals from HEDM-550X encoder
-- and output the value read
-- TODO Quelques modifications apportées depuis test avec les vraies codeuses
-- un nouveau test sera nécessaire (vérifier notamment le sens de parcours)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity hedm is
Port (
clk : in STD_LOGIC; -- Horloge, la fréquence n'importe pas
chA : in STD_LOGIC; -- Canal A
chB : in STD_LOGIC; -- Canal B
counts : out -- Integer;
);
end hedm;
architecture Behavioral of hedm is
signal counter : integer;
signal An, Bn : STD_LOGIC; -- Nouvelles valeurs de A et B stockées pour que les entrées soient lues une seule fois en début de cycle
signal Ap, Bp : STD_LOGIC; -- Précédentes valeurs de A et B pour détecter les front montant
begin
processInput : process(clk)
begin
if rising_edge(clk) then
Ap <= An;
Bp <= Bn;
An <= A;
Bn <= B;
-- On pourrait optimiser la logique avec un tableau de Karnaugh ou autres méthodes
-- de simplification d'algèbre de Boole, mais le "compilateur" pour FPGA fera un
-- tout aussi bon travail, on garde donc le code suivant pour la lisibilité
if (Ap = '0' and An = '1') then -- Front montant A
if (Bn = '0') then
counter <= counter + 1;
else
counter <= counter - 1;
end if;
elsif (Ap = '1' and An = '0') then -- Front descendant A
if (Bn = '1') then
counter <= counter + 1;
else
counter <= counter - 1;
end if;
elsif (Bp = '0' and Bn = '1') then -- Front montant B
if (An = '1') then
counter <= counter + 1;
else
counter <= counter - 1;
end if;
elsif (Bp = '1' and Bn = '0') then -- Front descendant B
if (An = '0') then
counter <= counter + 1;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
counts <= counter;
end Behavioral;

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# __ ____ _ __
# / |/ (_)_____________ / | / /___ _ ______ _
# / /|_/ / / ___/ ___/ __ \/ |/ / __ \ | / / __ `/
# / / / / / /__/ / / /_/ / /| / /_/ / |/ / /_/ /
# /_/ /_/_/\___/_/ \____/_/ |_/\____/|___/\__,_/
#
# Mercury User Constraints File
# Revision 1.0.142 (10/24/2012)
# Copyright (c) 2012 MicroNova, LLC
# www.micro-nova.com
# system oscillator
NET "CLK" LOC = "P43" | IOSTANDARD = LVTTL ;
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
# user LEDs and button
NET "LED<0>" LOC = "P13" | IOSTANDARD = LVTTL ;
NET "LED<1>" LOC = "P15" | IOSTANDARD = LVTTL ;
NET "LED<2>" LOC = "P16" | IOSTANDARD = LVTTL ;
NET "LED<3>" LOC = "P19" | IOSTANDARD = LVTTL ;
NET "BTN" LOC = "P41" | IOSTANDARD = LVTTL ;
# direct and global-clock I/O
NET "DIO<0>" LOC = "P20" | IOSTANDARD = LVTTL ;
NET "DIO<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
NET "DIO<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
NET "DIO<3>" LOC = "P34" | IOSTANDARD = LVTTL ;
NET "DIO<4>" LOC = "P35" | IOSTANDARD = LVTTL ;
NET "DIO<5>" LOC = "P36" | IOSTANDARD = LVTTL ;
NET "DIO<6>" LOC = "P37" | IOSTANDARD = LVTTL ;
NET "CIO<0>" LOC = "P40" | IOSTANDARD = LVTTL ;
NET "CIO<1>" LOC = "P44" | IOSTANDARD = LVTTL ;
# in-only pins
NET "INPIN<0>" LOC = "P68" | IOSTANDARD = LVTTL ;
NET "INPIN<1>" LOC = "P97" | IOSTANDARD = LVTTL ;
NET "INPIN<2>" LOC = "P7" | IOSTANDARD = LVTTL ;
NET "INPIN<3>" LOC = "P82" | IOSTANDARD = LVTTL ;
# level-shifted I/O
NET "IO<0>" LOC = "P59" | IOSTANDARD = LVTTL ;
NET "IO<1>" LOC = "P60" | IOSTANDARD = LVTTL ;
NET "IO<2>" LOC = "P61" | IOSTANDARD = LVTTL ;
NET "IO<3>" LOC = "P62" | IOSTANDARD = LVTTL ;
NET "IO<4>" LOC = "P64" | IOSTANDARD = LVTTL ;
NET "IO<5>" LOC = "P57" | IOSTANDARD = LVTTL ;
NET "IO<6>" LOC = "P56" | IOSTANDARD = LVTTL ;
NET "IO<7>" LOC = "P52" | IOSTANDARD = LVTTL ;
NET "IO<8>" LOC = "P50" | IOSTANDARD = LVTTL ;
NET "IO<9>" LOC = "P49" | IOSTANDARD = LVTTL ;
NET "IO<10>" LOC = "P85" | IOSTANDARD = LVTTL ;
NET "IO<11>" LOC = "P84" | IOSTANDARD = LVTTL ;
NET "IO<12>" LOC = "P83" | IOSTANDARD = LVTTL ;
NET "IO<13>" LOC = "P78" | IOSTANDARD = LVTTL ;
NET "IO<14>" LOC = "P77" | IOSTANDARD = LVTTL ;
NET "IO<15>" LOC = "P65" | IOSTANDARD = LVTTL ;
NET "IO<16>" LOC = "P70" | IOSTANDARD = LVTTL ;
NET "IO<17>" LOC = "P71" | IOSTANDARD = LVTTL ;
NET "IO<18>" LOC = "P72" | IOSTANDARD = LVTTL ;
NET "IO<19>" LOC = "P73" | IOSTANDARD = LVTTL ;
NET "IO<20>" LOC = "P5" | IOSTANDARD = LVTTL ;
NET "IO<21>" LOC = "P4" | IOSTANDARD = LVTTL ;
NET "IO<22>" LOC = "P6" | IOSTANDARD = LVTTL ;
NET "IO<23>" LOC = "P98" | IOSTANDARD = LVTTL ;
NET "IO<24>" LOC = "P94" | IOSTANDARD = LVTTL ;
NET "IO<25>" LOC = "P93" | IOSTANDARD = LVTTL ;
NET "IO<26>" LOC = "P90" | IOSTANDARD = LVTTL ;
NET "IO<27>" LOC = "P89" | IOSTANDARD = LVTTL ;
NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;
# memory & bus-switch
NET "switch_oen" LOC = "P3" | IOSTANDARD = LVTTL ;
NET "memory_oen" LOC = "P30" | IOSTANDARD = LVTTL ;
# flash/usb interface
NET "fpga_csn" LOC = "P39" | IOSTANDARD = LVTTL ;
NET "flash_csn" LOC = "P27" | IOSTANDARD = LVTTL ;
NET "spi_mosi" LOC = "P46" | IOSTANDARD = LVTTL ;
NET "spi_miso" LOC = "P51" | IOSTANDARD = LVTTL ;
NET "spi_sck" LOC = "P53" | IOSTANDARD = LVTTL ;
# ADC interface
NET "adc_miso" LOC = "P21" | IOSTANDARD = LVTTL ;
NET "adc_mosi" LOC = "P10" | IOSTANDARD = LVTTL ;
NET "adc_sck" LOC = "P9" | IOSTANDARD = LVTTL ;
NET "adc_csn" LOC = "P12" | IOSTANDARD = LVTTL ;
# CLOCK timing

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PROJECT = Principal
TARGET_PART = xc3s200a-vq100
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
PROGRAMMER = mercpcl
TOPLEVEL = Principal
VHDSOURCE = $(TOPLEVEL).vhd
CONSTRAINTS = mercury.ucf
# Implement design
# Allow unmatched LOC Constraints
NGDBUILD_OPTS += -aul
# Allow unmatched Timing Group Constraints
NGDBUILD_OPTS += -aut

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Subproject commit ba6d1c3a7acbec274282c59af11dae64eaec2618

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uart/source/uart.vhd