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https://github.com/RobotechLille/cdf2018-principal
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Ajout de deux capteurs à ultrasons
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@ -18,9 +18,11 @@ entity Principal is
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RIGHTCHA: in std_logic;
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RIGHTCHA: in std_logic;
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RIGHTCHB: in std_logic;
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RIGHTCHB: in std_logic;
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FRONTTRIGGER: out std_logic;
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FRONTTRIGGER: out std_logic;
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FRONTECHO: in std_logic;
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BACKTRIGGER: out std_logic;
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BACKTRIGGER: out std_logic;
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BACKECHO: in std_logic;
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FRONTLECHO: in std_logic;
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BACKLECHO: in std_logic;
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FRONTRECHO: in std_logic;
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BACKRECHO: in std_logic;
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ENAREF: out std_logic;
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ENAREF: out std_logic;
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ENA: out std_logic;
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ENA: out std_logic;
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IN1ENC: out std_logic;
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IN1ENC: out std_logic;
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@ -53,12 +55,20 @@ architecture Behavioral of Principal is
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end component;
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end component;
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-- Distance sensors
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-- Distance sensors
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signal front : integer := 0;
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signal frontMin : integer := 0;
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signal frontRaw : integer := 0;
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signal backMin : integer := 0;
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signal frontFinished : std_logic;
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signal frontL : integer := 0;
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signal back : integer := 0;
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signal frontLRaw : integer := 0;
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signal backRaw : integer := 0;
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signal frontLFinished : std_logic;
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signal backFinished : std_logic;
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signal backL : integer := 0;
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signal backLRaw : integer := 0;
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signal backLFinished : std_logic;
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signal frontR : integer := 0;
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signal frontRRaw : integer := 0;
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signal frontRFinished : std_logic;
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signal backR : integer := 0;
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signal backRRaw : integer := 0;
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signal backRFinished : std_logic;
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component hcsr04 IS
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component hcsr04 IS
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generic(
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generic(
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fFpga : INTEGER := fFpga
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fFpga : INTEGER := fFpga
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@ -187,39 +197,74 @@ begin
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counts => right
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counts => right
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);
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);
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frontCapt: hcsr04 port map (
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frontLCapt: hcsr04 port map (
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clk => CLK,
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clk => CLK,
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reset => reset,
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reset => reset,
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echo => FRONTECHO,
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echo => FRONTLECHO,
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distance => frontRaw,
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distance => frontLRaw,
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trigger => FRONTTRIGGER,
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trigger => FRONTTRIGGER,
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start => '1',
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start => '1',
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finished => frontFinished
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finished => frontLFinished
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);
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);
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frontFilter : FIR port map (
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frontLFilter : FIR port map (
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clock => CLK,
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clock => CLK,
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reset => reset,
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reset => reset,
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signalIn => frontRaw,
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signalIn => frontLRaw,
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signalOut => front,
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signalOut => frontL,
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start => frontFinished
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start => frontLFinished
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-- done => done
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-- done => done
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);
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);
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backCapt: hcsr04 port map (
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frontRCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => FRONTRECHO,
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distance => frontRRaw,
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-- trigger => FRONTTRIGGER,
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start => '1',
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finished => frontRFinished
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);
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frontRFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => frontRRaw,
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signalOut => frontR,
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start => frontRFinished
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-- done => done
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);
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backLCapt: hcsr04 port map (
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clk => CLK,
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clk => CLK,
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reset => reset,
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reset => reset,
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echo => BACKECHO,
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echo => BACKLECHO,
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distance => backRaw,
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distance => backLRaw,
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trigger => BACKTRIGGER,
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trigger => BACKTRIGGER,
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start => '1',
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start => '1',
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finished => backFinished
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finished => backLFinished
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);
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);
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backFilter : FIR port map (
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backLFilter : FIR port map (
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clock => CLK,
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clock => CLK,
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reset => reset,
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reset => reset,
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signalIn => backRaw,
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signalIn => backLRaw,
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signalOut => back,
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signalOut => backL,
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start => backFinished
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start => backLFinished
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-- done => done
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);
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backRCapt: hcsr04 port map (
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clk => CLK,
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reset => reset,
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echo => BACKRECHO,
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distance => backRRaw,
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-- trigger => BACKTRIGGER,
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start => '1',
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finished => backRFinished
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);
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backRFilter : FIR port map (
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clock => CLK,
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reset => reset,
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signalIn => backRRaw,
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signalOut => backR,
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start => backRFinished
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-- done => done
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-- done => done
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);
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);
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enAp : PWM port map (
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enAp : PWM port map (
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@ -263,14 +308,17 @@ begin
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rx => RX
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rx => RX
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);
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);
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frontMin <= frontLRaw when frontLRaw < frontRRaw else frontRRaw;
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backMin <= backLRaw when backLRaw < backRRaw else backRRaw;
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com: communication port map(
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com: communication port map(
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clock => CLK,
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clock => CLK,
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reset => reset,
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reset => reset,
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left => left,
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left => left,
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right => right,
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right => right,
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zerocoder => zerocoder,
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zerocoder => zerocoder,
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front => front,
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front => frontMin,
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back => back,
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back => backMin,
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txData => txData,
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txData => txData,
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txStb => txStb,
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txStb => txStb,
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txAck => txAck,
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txAck => txAck,
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@ -29,13 +29,13 @@ NET "RIGHTCHB" LOC = "P65" | IOSTANDARD = LVTTL ;
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NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ;
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NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ;
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# IO<17>
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# IO<17>
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NET "FRONTECHO" LOC = "P71" | IOSTANDARD = LVTTL ;
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NET "FRONTLECHO" LOC = "P71" | IOSTANDARD = LVTTL ;
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# IO<18>
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# IO<18>
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NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ;
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NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ;
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# IO<19>
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# IO<19>
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NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ;
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NET "BACKLECHO" LOC = "P73" | IOSTANDARD = LVTTL ;
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# IO<20>
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# IO<20>
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NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ;
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NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ;
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@ -61,5 +61,8 @@ NET "IN3END" LOC = "P90" | IOSTANDARD = LVTTL ;
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# IO<27>
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# IO<27>
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NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ;
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NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ;
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# NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ;
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# IO<28>
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# NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ;
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NET "FRONTRECHO" LOC = "P88" | IOSTANDARD = LVTTL ;
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# IO<29>
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NET "BACKRECHO" LOC = "P86" | IOSTANDARD = LVTTL ;
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