geoffrey/cdf2018-principal
geoffrey/cdf2018-principal
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Ajout de deux capteurs à ultrasons

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This commit is contained in:
Geoffrey Frogeye 2018-05-10 10:09:56 +02:00
parent d30f0ed548
commit f730d7b2b1
2 changed files with 81 additions and 30 deletions
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100
fpga/Principal.vhd
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@ -18,9 +18,11 @@ entity Principal is
RIGHTCHA: in std_logic; RIGHTCHA: in std_logic;
RIGHTCHB: in std_logic; RIGHTCHB: in std_logic;
FRONTTRIGGER: out std_logic; FRONTTRIGGER: out std_logic;
FRONTECHO: in std_logic;
BACKTRIGGER: out std_logic; BACKTRIGGER: out std_logic;
BACKECHO: in std_logic; FRONTLECHO: in std_logic;
BACKLECHO: in std_logic;
FRONTRECHO: in std_logic;
BACKRECHO: in std_logic;
ENAREF: out std_logic; ENAREF: out std_logic;
ENA: out std_logic; ENA: out std_logic;
IN1ENC: out std_logic; IN1ENC: out std_logic;
@ -53,12 +55,20 @@ architecture Behavioral of Principal is
end component; end component;
-- Distance sensors -- Distance sensors
signal front : integer := 0; signal frontMin : integer := 0;
signal frontRaw : integer := 0; signal backMin : integer := 0;
signal frontFinished : std_logic; signal frontL : integer := 0;
signal back : integer := 0; signal frontLRaw : integer := 0;
signal backRaw : integer := 0; signal frontLFinished : std_logic;
signal backFinished : std_logic; signal backL : integer := 0;
signal backLRaw : integer := 0;
signal backLFinished : std_logic;
signal frontR : integer := 0;
signal frontRRaw : integer := 0;
signal frontRFinished : std_logic;
signal backR : integer := 0;
signal backRRaw : integer := 0;
signal backRFinished : std_logic;
component hcsr04 IS component hcsr04 IS
generic( generic(
fFpga : INTEGER := fFpga fFpga : INTEGER := fFpga
@ -187,39 +197,74 @@ begin
counts => right counts => right
); );
frontCapt: hcsr04 port map ( frontLCapt: hcsr04 port map (
clk => CLK, clk => CLK,
reset => reset, reset => reset,
echo => FRONTECHO, echo => FRONTLECHO,
distance => frontRaw, distance => frontLRaw,
trigger => FRONTTRIGGER, trigger => FRONTTRIGGER,
start => '1', start => '1',
finished => frontFinished finished => frontLFinished
); );
frontFilter : FIR port map ( frontLFilter : FIR port map (
clock => CLK, clock => CLK,
reset => reset, reset => reset,
signalIn => frontRaw, signalIn => frontLRaw,
signalOut => front, signalOut => frontL,
start => frontFinished start => frontLFinished
-- done => done -- done => done
); );
backCapt: hcsr04 port map ( frontRCapt: hcsr04 port map (
clk => CLK,
reset => reset,
echo => FRONTRECHO,
distance => frontRRaw,
-- trigger => FRONTTRIGGER,
start => '1',
finished => frontRFinished
);
frontRFilter : FIR port map (
clock => CLK,
reset => reset,
signalIn => frontRRaw,
signalOut => frontR,
start => frontRFinished
-- done => done
);
backLCapt: hcsr04 port map (
clk => CLK, clk => CLK,
reset => reset, reset => reset,
echo => BACKECHO, echo => BACKLECHO,
distance => backRaw, distance => backLRaw,
trigger => BACKTRIGGER, trigger => BACKTRIGGER,
start => '1', start => '1',
finished => backFinished finished => backLFinished
); );
backFilter : FIR port map ( backLFilter : FIR port map (
clock => CLK, clock => CLK,
reset => reset, reset => reset,
signalIn => backRaw, signalIn => backLRaw,
signalOut => back, signalOut => backL,
start => backFinished start => backLFinished
-- done => done
);
backRCapt: hcsr04 port map (
clk => CLK,
reset => reset,
echo => BACKRECHO,
distance => backRRaw,
-- trigger => BACKTRIGGER,
start => '1',
finished => backRFinished
);
backRFilter : FIR port map (
clock => CLK,
reset => reset,
signalIn => backRRaw,
signalOut => backR,
start => backRFinished
-- done => done -- done => done
); );
enAp : PWM port map ( enAp : PWM port map (
@ -263,14 +308,17 @@ begin
rx => RX rx => RX
); );
frontMin <= frontLRaw when frontLRaw < frontRRaw else frontRRaw;
backMin <= backLRaw when backLRaw < backRRaw else backRRaw;
com: communication port map( com: communication port map(
clock => CLK, clock => CLK,
reset => reset, reset => reset,
left => left, left => left,
right => right, right => right,
zerocoder => zerocoder, zerocoder => zerocoder,
front => front, front => frontMin,
back => back, back => backMin,
txData => txData, txData => txData,
txStb => txStb, txStb => txStb,
txAck => txAck, txAck => txAck,

11
fpga/principal.ucf
View file

@ -29,13 +29,13 @@ NET "RIGHTCHB" LOC = "P65" | IOSTANDARD = LVTTL ;
NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ; NET "FRONTTRIGGER" LOC = "P70" | IOSTANDARD = LVTTL ;
# IO<17> # IO<17>
NET "FRONTECHO" LOC = "P71" | IOSTANDARD = LVTTL ; NET "FRONTLECHO" LOC = "P71" | IOSTANDARD = LVTTL ;
# IO<18> # IO<18>
NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ; NET "BACKTRIGGER" LOC = "P72" | IOSTANDARD = LVTTL ;
# IO<19> # IO<19>
NET "BACKECHO" LOC = "P73" | IOSTANDARD = LVTTL ; NET "BACKLECHO" LOC = "P73" | IOSTANDARD = LVTTL ;
# IO<20> # IO<20>
NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ; NET "ENAREF" LOC = "P5" | IOSTANDARD = LVTTL ;
@ -61,5 +61,8 @@ NET "IN3END" LOC = "P90" | IOSTANDARD = LVTTL ;
# IO<27> # IO<27>
NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ; NET "IN4" LOC = "P89" | IOSTANDARD = LVTTL ;
# NET "IO<28>" LOC = "P88" | IOSTANDARD = LVTTL ; # IO<28>
# NET "IO<29>" LOC = "P86" | IOSTANDARD = LVTTL ; NET "FRONTRECHO" LOC = "P88" | IOSTANDARD = LVTTL ;
# IO<29>
NET "BACKRECHO" LOC = "P86" | IOSTANDARD = LVTTL ;