This commit is contained in:
Geoffrey Frogeye 2017-05-19 05:49:51 +02:00
parent c8ada584c2
commit 2d6f3613b2
14 changed files with 1574 additions and 52 deletions

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@ -1,15 +1,10 @@
.equ PINA = 0x00 ; définition des adresses des ports .equ PINA = 0x00
.equ DDRA = 0x01 .equ DDRA = 0x01
.equ PORTA = 0x02 .equ PORTA = 0x02
.equ PINB = 0x03
.equ DDRB = 0x04
.equ PORTB = 0x05
.equ PINC = 0x06 .equ PINC = 0x06
.equ DDRC = 0x07 .equ DDRC = 0x07
.equ PORTC = 0x08 .equ PORTC = 0x08
.equ SREG = 0x3F
.equ WDTCSR = 0x60 .equ WDTCSR = 0x60
.equ TCCR0A = 0x24 .equ TCCR0A = 0x24
.equ TCCR0B = 0x25 .equ TCCR0B = 0x25
@ -29,10 +24,10 @@
; Vecteur RESET ; Vecteur RESET
jmp debut jmp debut
.org 0x0018 .org 0x0018 ; Interruption du watchdog
jmp wd jmp wd
.org 0x002E .org 0x002E ; Interruption du timer
jmp tm jmp tm
.org 0x0080 .org 0x0080
@ -60,20 +55,11 @@ debut:
cli cli
; SREG <- 0b10000000
LDI R16,0b10000000
STS SREG,R16
; Configuration des ports ; Configuration des ports
; DDRA@IO <- 0xFF ; DDRA@IO <- 0xFF
LDI R16,0xFF LDI R16,0xFF
OUT DDRA,R16 OUT DDRA,R16
; DDRB@IO <- 0xFF
LDI R16,0xFF
OUT DDRB,R16
; DDRC@IO <- 0xFF ; DDRC@IO <- 0xFF
LDI R16,0xFF LDI R16,0xFF
OUT DDRC,R16 OUT DDRC,R16
@ -89,11 +75,23 @@ debut:
STS WDTCSR,R16 STS WDTCSR,R16
; Timer toutes les 8-16ms ; Timer toutes les 2 ms
;TCCR0A@IO <- 0x00 ; TCCR0A@IO <- 0x00
;TCCR0B@IO <- 0x04 LDI R16,0x00
;TIMSK0 <- 0x01 OUT TCCR0A,R16
;TIFR0 <- 0x01
; TCCR0B@IO <- 0x04
LDI R16,0x04
OUT TCCR0B,R16
; TIMSK0 <- 0x01
LDI R16,0x01
STS TIMSK0,R16
; TIFR0 <- 0x01
LDI R16,0x01
STS TIFR0,R16
sei sei
boucle: boucle:
@ -104,7 +102,7 @@ boucle:
wd: wd:
inc d0 inc d0
; si d0 < 10 saut finwd ; si d0 < 10 saut affichage
LDS R16,d0 LDS R16,d0
PUSH R16 PUSH R16
LDI R16,10 LDI R16,10
@ -118,7 +116,7 @@ eti0:
eti1: eti1:
TST R16 TST R16
BREQ eti2 BREQ eti2
JMP finwd JMP affichage
eti2: eti2:
; d0 <- 0 ; d0 <- 0
@ -126,7 +124,7 @@ eti2:
STS d0,R16 STS d0,R16
inc d1 inc d1
; si d1 < 10 saut finwd ; si d1 < 10 saut affichage
LDS R16,d1 LDS R16,d1
PUSH R16 PUSH R16
LDI R16,10 LDI R16,10
@ -140,7 +138,7 @@ eti3:
eti4: eti4:
TST R16 TST R16
BREQ eti5 BREQ eti5
JMP finwd JMP affichage
eti5: eti5:
; d1 <- 0 ; d1 <- 0
@ -148,7 +146,7 @@ eti5:
STS d1,R16 STS d1,R16
inc d2 inc d2
; si d2 < 10 saut finwd ; si d2 < 10 saut affichage
LDS R16,d2 LDS R16,d2
PUSH R16 PUSH R16
LDI R16,10 LDI R16,10
@ -162,15 +160,63 @@ eti6:
eti7: eti7:
TST R16 TST R16
BREQ eti8 BREQ eti8
JMP finwd JMP affichage
eti8: eti8:
; d2 <- 0 ; d2 <- 0
LDI R16,0 LDI R16,0
STS d2,R16 STS d2,R16
finwd: affichage:
; PORTA@IO <- afficheur@ROM[d1] ; Affichage Simulateur
; PORTC@IO <- afficheur@ROM[d0]
; PORTB@IO <- afficheur@ROM[d1]
; PORTA@IO <- afficheur@ROM[d2]
reti
tm:
; PortC@IO <- select
LDS R16,select
OUT PortC,R16
; si select = 0x80 alors PortA@IO <- afficheur@ROM[d0]
LDS R16,select
PUSH R16
LDI R16,0x80
POP R17
CP R17,R16
BREQ eti9
CLR R16
RJMP eti10
eti9:
LDI R16,0x01
eti10:
TST R16
BREQ eti11
LDS R16,d0
LDI R30,low(afficheur<<1)
LDI R31,high(afficheur<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti11:
; si select = 0x40 alors PortA@IO <- afficheur@ROM[d1]
LDS R16,select
PUSH R16
LDI R16,0x40
POP R17
CP R17,R16
BREQ eti12
CLR R16
RJMP eti13
eti12:
LDI R16,0x01
eti13:
TST R16
BREQ eti14
LDS R16,d1 LDS R16,d1
LDI R30,low(afficheur<<1) LDI R30,low(afficheur<<1)
LDI R31,high(afficheur<<1) LDI R31,high(afficheur<<1)
@ -178,24 +224,23 @@ finwd:
ADD R30,R16 ADD R30,R16
ADC R31,R17 ADC R31,R17
LPM R16,Z LPM R16,Z
OUT PORTA,R16 OUT PortA,R16
eti14:
; PORTC@IO <- 0x40 ; si select = 0x20 alors PortA@IO <- afficheur@ROM[d2]
LDI R16,0x40 LDS R16,select
OUT PORTC,R16 PUSH R16
LDI R16,0x20
reti POP R17
CP R17,R16
tm: BREQ eti15
;PortC@IO <- select CLR R16
;si select = 0x80 alors PortA@IO <- afficheur@ROM[d0] RJMP eti16
;si select = 0x40 alors PortA@IO <- afficheur@ROM[d1] eti15:
;si select = 0x20 alors PortA@IO <- afficheur@ROM[d2] LDI R16,0x01
;lsl select eti16:
;si select = 0 alors select <- 0x20 TST R16
;PORTC@IO <- afficheur@ROM[d0] BREQ eti17
;PORTB@IO <- afficheur@ROM[d1]
; PORTA@IO <- afficheur@ROM[d2]
LDS R16,d2 LDS R16,d2
LDI R30,low(afficheur<<1) LDI R30,low(afficheur<<1)
LDI R31,high(afficheur<<1) LDI R31,high(afficheur<<1)
@ -203,10 +248,27 @@ tm:
ADD R30,R16 ADD R30,R16
ADC R31,R17 ADC R31,R17
LPM R16,Z LPM R16,Z
OUT PORTA,R16 OUT PortA,R16
eti17:
; PORTC@IO <- 0x40 lsl select
LDI R16,0x40 ; si select = 0 alors select <- 0x20
OUT PORTC,R16 LDS R16,select
PUSH R16
LDI R16,0
POP R17
CP R17,R16
BREQ eti18
CLR R16
RJMP eti19
eti18:
LDI R16,0x01
eti19:
TST R16
BREQ eti20
LDI R16,0x20
STS select,R16
eti20:
reti reti

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@ -1,4 +1,4 @@
.equ PINA = 0x00 ; définition des adresses des ports .equ PINA = 0x00
.equ DDRA = 0x01 .equ DDRA = 0x01
.equ PORTA = 0x02 .equ PORTA = 0x02
.equ PINC = 0x06 .equ PINC = 0x06

274
TP2/TP22b.asm Normal file
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@ -0,0 +1,274 @@
.equ PINA = 0x00
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINC = 0x06
.equ DDRC = 0x07
.equ PORTC = 0x08
.equ WDTCSR = 0x60
.equ TCCR0A = 0x24
.equ TCCR0B = 0x25
.equ TIMSK0 = 0x6E
.equ TIFR0 = 0x35
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.def d2 = r19
.def d1 = r20
.def d0 = r21
.def select = r22
.org 0x000
; Vecteur RESET
jmp debut
.org 0x0018 ; Interruption du watchdog
jmp wd
.org 0x002E ; Interruption du timer
jmp tm
.org 0x0080
afficheur:
.DB 0x7E, 0x0C, 0x37, 0x9F, 0x4D, 0xDB, 0xFB, 0x0E, 0xFF, 0xDF
; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
debut:
; d2 <- 0
LDI R16,0
STS d2,R16
; d1 <- 0
LDI R16,0
STS d1,R16
; d0 <- 0
LDI R16,0
STS d0,R16
; select <- 0b00100000
LDI R16,0b00100000
STS select,R16
cli
; Configuration des ports
; DDRA@IO <- 0xFF
LDI R16,0xFF
OUT DDRA,R16
; DDRC@IO <- 0xFF
LDI R16,0xFF
OUT DDRC,R16
; Watchdog toutes les secondes
; WDTCSR <- 0x10
LDI R16,0x10
STS WDTCSR,R16
; WDTCSR <- 0b01000110
LDI R16,0b01000110
STS WDTCSR,R16
; Timer toutes les 2 ms
; TCCR0A@IO <- 0x00
LDI R16,0x00
OUT TCCR0A,R16
; TCCR0B@IO <- 0x04
LDI R16,0x04
OUT TCCR0B,R16
; TIMSK0 <- 0x01
LDI R16,0x01
STS TIMSK0,R16
; TIFR0 <- 0x01
LDI R16,0x01
STS TIFR0,R16
sei
boucle:
sleep
; jump boucle
JMP boucle
wd:
inc d0
; si d0 < 10 saut affichage
LDS R16,d0
PUSH R16
LDI R16,10
POP R17
CP R17,R16
BRLO eti0
CLR R16
RJMP eti1
eti0:
LDI R16,0x01
eti1:
TST R16
BREQ eti2
JMP affichage
eti2:
; d0 <- 0
LDI R16,0
STS d0,R16
inc d1
; si d1 < 10 saut affichage
LDS R16,d1
PUSH R16
LDI R16,10
POP R17
CP R17,R16
BRLO eti3
CLR R16
RJMP eti4
eti3:
LDI R16,0x01
eti4:
TST R16
BREQ eti5
JMP affichage
eti5:
; d1 <- 0
LDI R16,0
STS d1,R16
inc d2
; si d2 < 10 saut affichage
LDS R16,d2
PUSH R16
LDI R16,10
POP R17
CP R17,R16
BRLO eti6
CLR R16
RJMP eti7
eti6:
LDI R16,0x01
eti7:
TST R16
BREQ eti8
JMP affichage
eti8:
; d2 <- 0
LDI R16,0
STS d2,R16
affichage:
; Affichage Simulateur
; PORTC@IO <- afficheur@ROM[d0]
; PORTB@IO <- afficheur@ROM[d1]
; PORTA@IO <- afficheur@ROM[d2]
reti
tm:
; PortC@IO <- select
LDS R16,select
OUT PortC,R16
; si select = 0b10000000 alors PortA@IO <- afficheur@ROM[d2]
LDS R16,select
PUSH R16
LDI R16,0b10000000
POP R17
CP R17,R16
BREQ eti9
CLR R16
RJMP eti10
eti9:
LDI R16,0x01
eti10:
TST R16
BREQ eti11
LDS R16,d2
LDI R30,low(afficheur<<1)
LDI R31,high(afficheur<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti11:
; si select = 0b01000000 alors PortA@IO <- afficheur@ROM[d1]
LDS R16,select
PUSH R16
LDI R16,0b01000000
POP R17
CP R17,R16
BREQ eti12
CLR R16
RJMP eti13
eti12:
LDI R16,0x01
eti13:
TST R16
BREQ eti14
LDS R16,d1
LDI R30,low(afficheur<<1)
LDI R31,high(afficheur<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti14:
; si select = 0b00100000 alors PortA@IO <- afficheur@ROM[d0]
LDS R16,select
PUSH R16
LDI R16,0b00100000
POP R17
CP R17,R16
BREQ eti15
CLR R16
RJMP eti16
eti15:
LDI R16,0x01
eti16:
TST R16
BREQ eti17
LDS R16,d0
LDI R30,low(afficheur<<1)
LDI R31,high(afficheur<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti17:
lsl select
; si select = 0 alors select <- 0b00100000
LDS R16,select
PUSH R16
LDI R16,0
POP R17
CP R17,R16
BREQ eti18
CLR R16
RJMP eti19
eti18:
LDI R16,0x01
eti19:
TST R16
BREQ eti20
LDI R16,0b00100000
STS select,R16
eti20:
reti

89
TP2/TP22b.txt Normal file
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@ -0,0 +1,89 @@
.equ PINA = 0x00
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINC = 0x06
.equ DDRC = 0x07
.equ PORTC = 0x08
.equ WDTCSR = 0x60
.equ TCCR0A = 0x24
.equ TCCR0B = 0x25
.equ TIMSK0 = 0x6E
.equ TIFR0 = 0x35
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.def d2 = r19
.def d1 = r20
.def d0 = r21
.def select = r22
.org 0x000
; Vecteur RESET
jmp debut
.org 0x0018 ; Interruption du watchdog
jmp wd
.org 0x002E ; Interruption du timer
jmp tm
.org 0x0080
afficheur:
.DB 0x7E, 0x0C, 0x37, 0x9F, 0x4D, 0xDB, 0xFB, 0x0E, 0xFF, 0xDF
; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
debut:
d2 <- 0
d1 <- 0
d0 <- 0
select <- 0b00100000
cli
; Configuration des ports
DDRA@IO <- 0xFF
DDRC@IO <- 0xFF
; Watchdog toutes les secondes
WDTCSR <- 0x10
WDTCSR <- 0b01000110
; Timer toutes les 2 ms
TCCR0A@IO <- 0x00
TCCR0B@IO <- 0x04
TIMSK0 <- 0x01
TIFR0 <- 0x01
sei
boucle:
sleep
jump boucle
wd:
inc d0
si d0 < 10 saut affichage
d0 <- 0
inc d1
si d1 < 10 saut affichage
d1 <- 0
inc d2
si d2 < 10 saut affichage
d2 <- 0
affichage:
; Affichage Simulateur
; PORTC@IO <- afficheur@ROM[d0]
; PORTB@IO <- afficheur@ROM[d1]
; PORTA@IO <- afficheur@ROM[d2]
reti
tm:
PortC@IO <- select
si select = 0b10000000 alors PortA@IO <- afficheur@ROM[d2]
si select = 0b01000000 alors PortA@IO <- afficheur@ROM[d1]
si select = 0b00100000 alors PortA@IO <- afficheur@ROM[d0]
lsl select
si select = 0 alors select <- 0b00100000
reti

81
TP3/TP30.asm Normal file
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@ -0,0 +1,81 @@
.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.org 0x000
; Vecteur RESET
jmp debut
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
; DDRA@IO <- 0xFF
LDI R16,0xFF
OUT DDRA,R16
; ADMUX <- 0b01100000
LDI R16,0b01100000
STS ADMUX,R16
; ADCSRB <- 0b00000000
LDI R16,0b00000000
STS ADCSRB,R16
; ADCSRA <- 0b11100111
LDI R16,0b11100111
STS ADCSRA,R16
boucle:
; PORTA@IO <- codeAff@ROM[ADCH/25]
LDS R16,ADCH
LDI R17,25
SER R18
eti0:
INC R18
SUB R16,R17
BRCC eti0
MOV R16,R18
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PORTA,R16
jmp boucle

52
TP3/TP30.txt Normal file
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@ -0,0 +1,52 @@
.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.org 0x000
; Vecteur RESET
jmp debut
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
DDRA@IO <- 0xFF
ADMUX <- 0b01100000
ADCSRB <- 0b00000000
ADCSRA <- 0b11100111
boucle:
PORTA@IO <- codeAff@ROM[ADCH/25]
jmp boucle

88
TP3/TP30b.asm Normal file
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@ -0,0 +1,88 @@
.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.org 0x000
; Vecteur RESET
jmp debut
.org 0x003A
jmp irqadc
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
; DDRA@IO <- 0xFF
LDI R16,0xFF
OUT DDRA,R16
; ADMUX <- 0b01100000
LDI R16,0b01100000
STS ADMUX,R16
; ADCSRB <- 0b00000000
LDI R16,0b00000000
STS ADCSRB,R16
; ADCSRA <- 0b11101111
LDI R16,0b11101111
STS ADCSRA,R16
sei
boucle:
sleep
jmp boucle
irqadc:
; PORTA@IO <- codeAff@ROM[ADCH/27]
LDS R16,ADCH
LDI R17,27
SER R18
eti0:
INC R18
SUB R16,R17
BRCC eti0
MOV R16,R18
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PORTA,R16
reti

59
TP3/TP30b.txt Normal file
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@ -0,0 +1,59 @@
.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.org 0x000
; Vecteur RESET
jmp debut
.org 0x003A
jmp irqadc
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
DDRA@IO <- 0xFF
ADMUX <- 0b01100000
ADCSRB <- 0b00000000
ADCSRA <- 0b11101111
sei
boucle:
sleep
jmp boucle
irqadc:
PORTA@IO <- codeAff@ROM[ADCH/27]
reti

133
TP3/TP31.asm Normal file
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@ -0,0 +1,133 @@
.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINB = 0x03
.equ DDRB = 0x04
.equ PORTB = 0x05
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.def temp = r20
.org 0x000
; Vecteur RESET
jmp debut
.org 0x003A
jmp irqadc
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
; DDRA@IO <- 0xFF
LDI R16,0xFF
OUT DDRA,R16
; DDRB@IO <- 0xFF
LDI R16,0xFF
OUT DDRB,R16
; ADMUX <- 0b01100000
LDI R16,0b01100000
STS ADMUX,R16
; ADCSRB <- 0b00000000
LDI R16,0b00000000
STS ADCSRB,R16
; ADCSRA <- 0b11101111
LDI R16,0b11101111
STS ADCSRA,R16
sei
boucle:
sleep
jmp boucle
irqadc:
; temp <- ADCH / 8
LDS R16,ADCH
LDI R17,8
SER R18
eti0:
INC R18
SUB R16,R17
BRCC eti0
MOV R16,R18
STS temp,R16
; PORTA@IO <- codeAff@ROM[temp/10]
LDS R16,temp
LDI R17,10
SER R18
eti1:
INC R18
SUB R16,R17
BRCC eti1
MOV R16,R18
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PORTA,R16
; PORTB@IO <- codeAff@ROM[temp-(temp/10)*10]
LDS R16,temp
PUSH R16
LDS R16,temp
LDI R17,10
SER R18
eti2:
INC R18
SUB R16,R17
BRCC eti2
MOV R16,R18
LDI R17,10
MUL R16,R17
MOV R16,R0
MOV R17,R16
POP R16
SUB R16,R17
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PORTB,R16
reti

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.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINB = 0x03
.equ DDRB = 0x04
.equ PORTB = 0x05
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.def temp = r20
.org 0x000
; Vecteur RESET
jmp debut
.org 0x003A
jmp irqadc
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
DDRA@IO <- 0xFF
DDRB@IO <- 0xFF
ADMUX <- 0b01100000
ADCSRB <- 0b00000000
ADCSRA <- 0b11101111
sei
boucle:
sleep
jmp boucle
irqadc:
temp <- ADCH / 8
PORTA@IO <- codeAff@ROM[temp/10]
PORTB@IO <- codeAff@ROM[temp-(temp/10)*10]
reti

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.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINC = 0x06
.equ DDRC = 0x07
.equ PORTC = 0x08
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ TCCR0A = 0x24
.equ TCCR0B = 0x25
.equ TIMSK0 = 0x6E
.equ TIFR0 = 0x35
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.def d2 = r19
.def d1 = r20
.def d0 = r21
.def select = r22
.def temp = r23
.org 0x000
; Vecteur RESET
jmp debut
.org 0x002E ; Interruption du timer
jmp tm
.org 0x003A
jmp irqadc
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
cli
; DDRA@IO <- 0xFF
LDI R16,0xFF
OUT DDRA,R16
; DDRC@IO <- 0xFF
LDI R16,0xFF
OUT DDRC,R16
; ADMUX <- 0b01100001
LDI R16,0b01100001
STS ADMUX,R16
; ADCSRB <- 0b00000000
LDI R16,0b00000000
STS ADCSRB,R16
; ADCSRA <- 0b11101111
LDI R16,0b11101111
STS ADCSRA,R16
; Timer toutes les 2 ms
; TCCR0A@IO <- 0x00
LDI R16,0x00
OUT TCCR0A,R16
; TCCR0B@IO <- 0x04
LDI R16,0x04
OUT TCCR0B,R16
; TIMSK0 <- 0x01
LDI R16,0x01
STS TIMSK0,R16
; TIFR0 <- 0x01
LDI R16,0x01
STS TIFR0,R16
sei
; d2 <- 1
LDI R16,1
STS d2,R16
; d1 <- 2
LDI R16,2
STS d1,R16
; d0 <- 3
LDI R16,3
STS d0,R16
; select <- 0b00100000
LDI R16,0b00100000
STS select,R16
boucle:
sleep
jmp boucle
irqadc:
; temp <- ADCH
LDS R16,ADCH
STS temp,R16
; d2 <- temp / 100
LDS R16,temp
LDI R17,100
SER R18
eti0:
INC R18
SUB R16,R17
BRCC eti0
MOV R16,R18
STS d2,R16
; d1 <- temp / 10 - (temp / 100) * 10
LDS R16,temp
LDI R17,10
SER R18
eti1:
INC R18
SUB R16,R17
BRCC eti1
MOV R16,R18
PUSH R16
LDS R16,temp
LDI R17,100
SER R18
eti2:
INC R18
SUB R16,R17
BRCC eti2
MOV R16,R18
LDI R17,10
MUL R16,R17
MOV R16,R0
MOV R17,R16
POP R16
SUB R16,R17
STS d1,R16
; d0 <- temp - temp/10*10
LDS R16,temp
PUSH R16
LDS R16,temp
LDI R17,10
SER R18
eti3:
INC R18
SUB R16,R17
BRCC eti3
MOV R16,R18
LDI R17,10
MUL R16,R17
MOV R16,R0
MOV R17,R16
POP R16
SUB R16,R17
STS d0,R16
reti
tm:
; PortC@IO <- select
LDS R16,select
OUT PortC,R16
; si select = 0b10000000 alors PortA@IO <- codeAff@ROM[d2]
LDS R16,select
PUSH R16
LDI R16,0b10000000
POP R17
CP R17,R16
BREQ eti4
CLR R16
RJMP eti5
eti4:
LDI R16,0x01
eti5:
TST R16
BREQ eti6
LDS R16,d2
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti6:
; si select = 0b01000000 alors PortA@IO <- codeAff@ROM[d1]
LDS R16,select
PUSH R16
LDI R16,0b01000000
POP R17
CP R17,R16
BREQ eti7
CLR R16
RJMP eti8
eti7:
LDI R16,0x01
eti8:
TST R16
BREQ eti9
LDS R16,d1
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti9:
; si select = 0b00100000 alors PortA@IO <- codeAff@ROM[d0]
LDS R16,select
PUSH R16
LDI R16,0b00100000
POP R17
CP R17,R16
BREQ eti10
CLR R16
RJMP eti11
eti10:
LDI R16,0x01
eti11:
TST R16
BREQ eti12
LDS R16,d0
LDI R30,low(codeAff<<1)
LDI R31,high(codeAff<<1)
CLR R17
ADD R30,R16
ADC R31,R17
LPM R16,Z
OUT PortA,R16
eti12:
lsl select
; si select = 0 alors select <- 0b00100000
LDS R16,select
PUSH R16
LDI R16,0
POP R17
CP R17,R16
BREQ eti13
CLR R16
RJMP eti14
eti13:
LDI R16,0x01
eti14:
TST R16
BREQ eti15
LDI R16,0b00100000
STS select,R16
eti15:
reti

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.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINC = 0x06
.equ DDRC = 0x07
.equ PORTC = 0x08
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ TCCR0A = 0x24
.equ TCCR0B = 0x25
.equ TIMSK0 = 0x6E
.equ TIFR0 = 0x35
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.def d2 = r19
.def d1 = r20
.def d0 = r21
.def select = r22
.def temp = r23
.org 0x000
; Vecteur RESET
jmp debut
.org 0x002E ; Interruption du timer
jmp tm
.org 0x003A
jmp irqadc
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
cli
DDRA@IO <- 0xFF
DDRC@IO <- 0xFF
ADMUX <- 0b01100001
ADCSRB <- 0b00000000
ADCSRA <- 0b11101111
; Timer toutes les 2 ms
TCCR0A@IO <- 0x00
TCCR0B@IO <- 0x04
TIMSK0 <- 0x01
TIFR0 <- 0x01
sei
d2 <- 1
d1 <- 2
d0 <- 3
select <- 0b00100000
boucle:
sleep
jmp boucle
irqadc:
temp <- ADCH
d2 <- temp / 100
d1 <- temp / 10 - (temp / 100) * 10
d0 <- temp - temp/10*10
reti
tm:
PortC@IO <- select
si select = 0b10000000 alors PortA@IO <- codeAff@ROM[d2]
si select = 0b01000000 alors PortA@IO <- codeAff@ROM[d1]
si select = 0b00100000 alors PortA@IO <- codeAff@ROM[d0]
lsl select
si select = 0 alors select <- 0b00100000
reti

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.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINB = 0x03
.equ DDRB = 0x04
.equ PORTB = 0x05
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.def temp = r20
.def consigne = r21
.org 0x000
; Vecteur RESET
jmp debut
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
; DDRA@IO <- 0b01111111
LDI R16,0b01111111
OUT DDRA,R16
; DDRB@IO <- 0xFF
LDI R16,0xFF
OUT DDRB,R16
; ADCSRB <- 0b00000000
LDI R16,0b00000000
STS ADCSRB,R16
boucle:
; ADMUX <- 0b01100000
LDI R16,0b01100000
STS ADMUX,R16
; ADCSRA <- 0b11100111
LDI R16,0b11100111
STS ADCSRA,R16
;ADCSRB <- 0b01000010
attente1:
; si (ADCSRA & 0b00010000) = 0 saut attente1
LDS R16,ADCSRA
ANDI R16,0b00010000
PUSH R16
LDI R16,0
POP R17
CP R17,R16
BREQ eti0
CLR R16
RJMP eti1
eti0:
LDI R16,0x01
eti1:
TST R16
BREQ eti2
JMP attente1
eti2:
; r5 <- ADCH
LDS R16,ADCH
MOV R5,R16
;ADCSRA <- ADCSRA & 0b11101111
;consigne <- ADCH / 8 + 20
;si (PORTA@IO & 0b10000000) = 0 alors consigne <- 12
; ADMUX <- 0b01100001
LDI R16,0b01100001
STS ADMUX,R16
; ADCSRA <- 0b11100111
LDI R16,0b11100111
STS ADCSRA,R16
;ADCSRB <- 0b01000010
attente2:
; si (ADCSRA & 0b00010000) = 0 saut attente2
LDS R16,ADCSRA
ANDI R16,0b00010000
PUSH R16
LDI R16,0
POP R17
CP R17,R16
BREQ eti3
CLR R16
RJMP eti4
eti3:
LDI R16,0x01
eti4:
TST R16
BREQ eti5
JMP attente2
eti5:
; r6 <- ADCH
LDS R16,ADCH
MOV R6,R16
;ADCSRA <- ADCSRA & 0b11101111
;temp <- ADCH / 4
;PORTA@IO <- codeAff@ROM[temp/20]
;PORTB@IO <- codeAff@ROM[temp-(temp/20)*20]
;si consigne - 1 > temp alors PORTB@IO <- PORTB@IO | 0b10000000
;si consigne + 1 < temp alors PORTB@IO <- PORTB@IO & 0b01111111
;PORTB@IO <- PORTB@IO | 0b10000000
jmp boucle

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.equ PINA = 0x00 ; définition des adresses des ports
.equ DDRA = 0x01
.equ PORTA = 0x02
.equ PINB = 0x03
.equ DDRB = 0x04
.equ PORTB = 0x05
.equ RAMEND = 0x21FF
.equ SPH = 0x3E ; initialisation de la pile
.equ SPL = 0x3D
.equ SREG = 0x3F
.equ ADMUX = 0x7C
.equ ADCSRB = 0x7B
.equ ADCSRA = 0x7A
.equ ADCH = 0x79
.equ ADCL = 0x78
.def temp = r20
.def consigne = r21
.org 0x000
; Vecteur RESET
jmp debut
.org 0x0080
codeAff:
.db 0b1111110, 0b001100
.db 0b0110111, 0b0011111
.db 0b1001101, 0b1011011
.db 0b1111011, 0b0001110
.db 0b1111111, 0b1011111
debut:
ldi r28, low(RAMEND)
ldi r29, high(RAMEND)
out SPL, r28
out SPH, r29
DDRA@IO <- 0b01111111
DDRB@IO <- 0xFF
ADCSRB <- 0b00000000
boucle:
ADMUX <- 0b01100000
ADCSRA <- 0b11100111
;ADCSRB <- 0b01000010
attente1:
si (ADCSRA & 0b00010000) = 0 saut attente1
r5 <- ADCH
;ADCSRA <- ADCSRA & 0b11101111
;consigne <- ADCH / 8 + 20
;si (PORTA@IO & 0b10000000) = 0 alors consigne <- 12
ADMUX <- 0b01100001
ADCSRA <- 0b11100111
;ADCSRB <- 0b01000010
attente2:
si (ADCSRA & 0b00010000) = 0 saut attente2
r6 <- ADCH
;ADCSRA <- ADCSRA & 0b11101111
;temp <- ADCH / 4
;PORTA@IO <- codeAff@ROM[temp/20]
;PORTB@IO <- codeAff@ROM[temp-(temp/20)*20]
;si consigne - 1 > temp alors PORTB@IO <- PORTB@IO | 0b10000000
;si consigne + 1 < temp alors PORTB@IO <- PORTB@IO & 0b01111111
;PORTB@IO <- PORTB@IO | 0b10000000
jmp boucle