cdf2018-principal/fpga/project.cfg

PROJECT = Principal
TARGET_PART = xc3s200a-vq100
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
PROGRAMMER = mercpcl

TOPLEVEL = Principal
# Prod
VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd fir.vhd
CONSTRAINTS = principal.ucf
Commit initial 2018-02-07 17:57:01 +01:00			`PROJECT = Principal`
			`TARGET_PART = xc3s200a-vq100`
			`XILINX = /opt/Xilinx/14.7/ISE_DS/ISE`
			`PROGRAMMER = mercpcl`

			`TOPLEVEL = Principal`
Communication du FPGA : Ajout des bases 2018-02-21 16:58:43 +01:00			`# Prod`
FPGA : Filtre 2018-02-28 12:06:11 +01:00			`VHDSOURCE = $(TOPLEVEL).vhd communication.vhd uart.vhd hedm.vhd hcsr04.vhd fir.vhd`
FPGA : HCSR04 et améliorations 2018-02-27 19:33:58 +01:00			`CONSTRAINTS = principal.ucf`